SL811HS_07 CYPRESS [Cypress Semiconductor], SL811HS_07 Datasheet - Page 8

• Manufacturer Part Number: SL811HS_07
• Description: Embedded USB Host/Slave Controller
• Manufacturer: CYPRESS [Cypress Semiconductor]

Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with control bits defined
as follows.
Table 11. Control Register 1 [Address 05h]
At powe -up this register is cleared to all zeros.
Low-power Modes [Bit 6 Control Register, Address 05h]
When bit 6 (Suspend) is set to ’1’, the power of the transmit
transceiver is turned off, the internal RAM is in suspend mode,
and the internal clocks are disabled.
Note Any activity on the USB bus (i.e., K-State, etc.) resumes
normal operation. To resume normal operation from the CPU
side, a Data Write cycle (i.e., A0 set HIGH for a Data Write
cycle) is done. This is a special case and not a normal direct
write where the address is first written and then the data. To
resume normal operation from the CPU side, you must do a
Data Write cycle only.
Low Speed/Full Speed Modes [Bit 5 Control Register 1,
Address 05h]
The SL811HS is designed to communicate with either full- or
low speed devices. At power up bit 5 is LOW, i.e., for full
speed. There are two cases when communicating with a low
speed device. When a low speed device is connected directly
to the SL811HS, bit 5 of Register 05h is set to ’1’ and bit 6 of
register 0Fh, Polarity Swap, is set to ’1’ in order to change the
polarity of D+ and D–. When a low speed device is connected
via a HUB to SL811HS, bit 5 of Register 05h is set to ’0’ and
bit 6 of register 0Fh is set to ’0’ in order to keep the polarity of
D+ and D– for full speed. In addition, make sure that bit 7 of
USB-A/USB-B Host Control registers [00h, 08h] is set to ’1’ for
preamble generation.
J-K Programming States [Bits 4 and 3 of Control Register
1, Address 05h]
The J-K force state control and USB Engine Reset bits are
used to generate a USB reset condition. Forcing K-state is
Document 38-08008 Rev. *D
Notes
2. Force K-State for low speed.
3. Force J-State for low speed.
Bit Position
Reserved
Bit 7
7
6
5
4
3
2
1
0
Reserved
Suspend
USB Speed
J-K state force
USB Engine Reset
Reserved
Reserved
SOF ena/dis
Bit Name
Suspend
Bit 6
USB Speed
Bit 5
‘0’
’1’ = enable, ’0’ = disable.
’0’ setup for full speed, ’1’ setup low speed.
See
USB Engine reset = ’1’. Normal set ’0’.
When a device is detected, the first thing that to do is to send it a USB Reset to force it into
its default address of zero. The USB 2.0 specification states that for a root hub a device
must be reset for a minimum of 50 mS.
Some existing firmware examples set bit 2, but it is not necessary.
’1’ = enable auto Hardware SOF generation; ’0’ = disable.
In the SL811HS, bit 0 is used to enable hardware SOF autogeneration. The generation of
SOFs continues when set to ‘0’, but SOF tokens are not output to USB.
‘0’
Function
Table
J-K state force
12.
Bit 4
USB Engine
used for Peripheral device remote wake up, resume, and other
modes. These two bits are set to zero on power up.
Table 12. Control Register 1 Address 05h – Bits 3 and 4
USB Reset Sequence
After a device is detected, write 08h to the Control register
(05h) to initiate the USB reset, then wait for the USB reset time
(root hub should be 50 ms) and additionally some types of
devices such as a Forced J-state. Lastly, set the Control
register (05h) back to 0h. After the reset is complete, the
auto-SOF generation is enabled.
SOF Packet Generation
The SL811HS automatically computes the frame number and
CRC5 by hardware. No CRC or SOF generation is required by
external firmware for the SL811HS, although it can be done by
sending an SOF PID in the Host PID, Device Endpoint register.
To enable SOF generation, assuming host mode is configured:
1. Set up the SOF interval in registers 0x0F and 0x0E.
2. Enable the SOF hardware generation in this register by
3. Set the Arm bit in the USB-A Host Control register.
Bit 4
Reset
0
0
1
1
setting bit 0 = ‘1’.
Bit 3
Bit 3
0
1
0
1
Reserved
Function
Normal operating mode
Force USB Reset, D+ and D– are set LOW (SE0)
Force J-State, D+ set HIGH, D– set LOW
Force K-State, D– set HIGH, D+ set LOW
Bit 2
Reserved
Bit 1
SL811HS
SOF ena/dis
Page 8 of 32
Bit 0
[2]
[3]
[+] Feedback
[+] Feedback