SL811HS_07 CYPRESS [Cypress Semiconductor], SL811HS_07 Datasheet - Page 5

• Manufacturer Part Number: SL811HS_07
• Description: Embedded USB Host/Slave Controller
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document 38-08008 Rev. *D
USB-A/USB-B Host Control Registers [Address = 00h, 08h] .
Table 3. USB-A/USB-B Host Control Register Definition [Address 00h, 08h]
Once the other SL811HS Control registers are configured (registers 01h-04h or 09h-0Ch) the Host Control register is programmed
to initiate the USB transfer. This register initiates the transfer when the Enable and Arm bit are set as described above.
USB-A/USB-B Host Base Address [Address = 01h, 09h] .
Table 4. USB-A/USB-B Host Base Address Definition [Address 01h, 09h]
The USB-A/B Base Address is a pointer to the SL811HS memory buffer location for USB reads and writes. When transferring
data OUT (Host to Device), the USB-A and USB-B Host Base Address registers can be set up before setting ARM on the USB-A
or USB-B Host Control register. When using a double buffer scheme, the Host Base Address could be set up with the first buffer
used for DATA0 data and the other for DATA1 data.
Bit Position
Preamble
HBADD7
Bit 7
Bit 7
7
6
5
4
3
2
1
0
Preamble
Data Toggle Bit
SyncSOF
ISO
Reserved
Direction
Enable
Arm
Data Toggle Bit
Bit Name
HBADD6
Bit 6
Bit 6
SyncSOF
HBADD5
If bit = ’1’ a preamble token is transmitted before transfer of low speed packet. If bit = ’0’,
preamble generation is disabled.
’0’ if DATA0, ’1’ if DATA1 (only used for OUT tokens in host mode).
’1’ = Synchronize with the SOF transfer when operating in FS only.
The SL811HS uses bit 5 to enable transfer of a data packet after a SOF packet is transmitted.
When bit 5 = ‘1’, the next enabled packet is sent after next SOF. If bit 5 = ‘0’ the next packet
is sent immediately if the SIE is free. If operating in low speed, do not set this bit.
When set to ’1’, this bit allows Isochronous mode for this packet.
Bit 3 is reserved for future use.
When equal to ’1’ transmit (OUT). When equal to ’0’ receive (IN).
If Enable = ’1’, this bit allows transfers to occur. If Enable = ’0’, USB transactions are ignored.
The Enable bit is used in conjunction with the Arm bit (bit 0 of this register) for USB transfers.
Allows enabled transfers when Arm = ’1’. Cleared to ’0’ when transfer is complete (when
Done Interrupt is asserted).
Bit 5
Bit 5
Function
• The SL811HS automatically generates preamble packets when bit 7 is set. This bit is only
• When SL811HS communicates directly to a low speed device:
used to send packets to a low speed device through a hub. To communicate to a full
speed device, this bit is set to ‘0’. For example, when SL811HS communicates to a low
speed device via the HUB:
— Set SL811HS SIE to operate at full speed, i.e., bit 5 of register 05h (Control Register 1)
— Set bit 6 of register 0Fh (Control Register 2) = ’0’. Set correct polarity of DATA+ and
— Set bit 7, Preamble bit, = ’1’ in the Host Control register.
— Set bit 5 of register 05h (Control Register 1) = ’1’.
— Set bit 6 of register 0Fh (Control Register 2) = ’1’, DATA+ and DATA– polarity for low
— The state of bit 7 is ignored in this mode.
= ’0’.
DATA– state for full speed.
speed.
HBADD4
Bit 4
Bit 4
ISO
Reserved
HBADD3
Bit 3
Bit 3
HBADD2
Direction
Bit 2
Bit 2
HBADD1
Enable
Bit 1
Bit 1
SL811HS
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HBADD0
Bit 0
Bit 0
Arm
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