SL811HS_07 CYPRESS [Cypress Semiconductor], SL811HS_07 Datasheet - Page 29
SL811HS_07
Manufacturer Part Number
SL811HS_07
Description
Embedded USB Host/Slave Controller
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.SL811HS_07.pdf
(32 pages)
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Document 38-08008 Rev. *D
DMA Read Cycle
Note Data is held until nDACK goes high regardless of state of nREAD.
Reset Timing
Note Clock is 48 MHz nominal.
t
t
RESET
IOACT
tdack
tddrdlo
tdckdr
tdrdp
tdhld
tddaccs
tdrdack
tdakrq
trdcycle
Parameter
Parameter
n D R Q
D 0-D 7
n R D
n D A C K
nRD or nWR
nRst Pulse width
nRst HIGH to nRD or nWR active
nDACK low
nDACK to nRD low delay
nDACK low to nDRQ high delay
nRD pulse width
Date hold after nDACK high
Data access from nDACK low
nRD high to nDACK high
nDRQ low after nDACK high
DMA Read Cycle Time
nRST
Description
tdaccs
Description
treset
S L 811 D M A R E A D C Y C L E T IM IN G
SL811 DMA Read Cycle Timing
Reset Timing
tdckdr
tddrdlo
100 ns
150 ns
90 ns
85 ns
Min.
0 ns
5 ns
5 ns
0 ns
5 ns
tdrdp
16 clocks
16 clocks
tioact
tdack
Min.
D A T A
Typ.
Typ.
tdakrq
tdhld
SL811HS
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