SL811HS_07 CYPRESS [Cypress Semiconductor], SL811HS_07 Datasheet
SL811HS_07
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SL811HS_07 Summary of contents
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SL811HS Embedded USB Host/Slave Controller Features • First USB Host/Slave controller for embedded systems in the market with a standard microprocessor bus interface • Supports both full speed (12 Mbps) and low speed (1.5 Mbps) USB transfer in both master ...
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Data Port, Microprocessor Interface The SL811HS microprocessor interface provides an 8-bit bidirectional data path along with appropriate control lines to interface to external processors or controllers. Programmed I/O or memory mapped I/O designs are supported through the 8-bit interface, chip ...
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PLL Clock Generator Either a 12 MHz MHz external crystal is used with the [1] SL811HS . Two pins, X1 and X2, are provided to connect a low cost crystal circuit to the device as shown in ...
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Slave Mode Registers” on page 12 register definitions). Access to the registers are through the microprocessor interface similar to normal RAM accesses (see “Bus Interface Timing Requirements” on page provide control and status information for USB transactions. Any write ...
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USB-A/USB-B Host Control Registers [Address = 00h, 08h] . Table 3. USB-A/USB-B Host Control Register Definition [Address 00h, 08h] Bit 7 Bit 6 Bit 5 Preamble Data Toggle Bit SyncSOF Bit Position Bit Name Function 7 Preamble If bit = ...
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USB-A/USB-B Host Base Length [Address = 02h, 0Ah]. Table 5. USB-A / USB-B Host Base Length Definition [Address 02h, 0Ah] Bit 7 Bit 6 Bit 5 HBL7 HBL6 HBL5 The USB A/B Host Base Length register contains the maximum packet ...
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USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch]. This register has two different functions depending on whether it is read or written. When read, this register contains the number of bytes remaining (from Host Base ...
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Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with control bits defined as follows. Table 11. Control Register 1 [Address 05h] Bit 7 Bit 6 Bit 5 Reserved Suspend USB Speed Bit Position Bit ...
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Interrupt Enable Register [Address = 06h]. The SL811HS provides an Interrupt Request Output, which is activated for a number of conditions. The Interrupt Enable register allows the user to select conditions that result in an interrupt that is issued to ...
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Interrupt Status Register, Address [Address = 0Dh]. The Interrupt Status register is a READ/WRITE register providing interrupt status. Interrupts are cleared by writing to this register. To clear a specific interrupt, the register is written with corre- sponding bit set ...
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Table 16. SOF Counter LOW Address when Written [Address 0Eh] Bit 7 Bit 6 Bit 5 SOF7 SOF6 SOF5 Example: To set up SOF for 1 ms interval, SOF counter register 0Eh should be set to E0h. SOF Counter High/Control ...
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SL811HS Slave Mode Registers Table 19. SL811HS Slave/Peripheral Mode Register Summary Register Name EP 0 – Control Register 00h EP Base Address Register 01h EP Base Length Register 02h EP Packet Status Register 03h ...
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Endpoint Control Registers Endpoint n Control Register [Address a = (EP# * 10h (EP# * 10h)+8]. Each endpoint set has a Control register defined as follows: Table 22. Endpoint Control Register [Address EP0a/b:00h/08h, EP1a/b:10h/18h, EP2a/b:20h/28h, EP3a/b:30h/38h ...
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Endpoint Packet Status [Address a = (EP# * 10h)+ (EP# * 10h)+Bh]. The packet status contains information relative to the packet that is received or transmitted. The register is defined as follows: Table 25. Endpoint Packet Status Reg ...
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Control Register 1, Address [05h]. The Control register enables or disables USB transfers and DMA operations with control bits. Table 28. Control Register 1 [Address 05h Reserved STBYD SPSEL Bit Position Bit Name Function 7 Reserved Reserved ...
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Interrupt Enable Register, Address [06h] . The provides an Interrupt Request Output that is activated resulting from a number of conditions. The Interrupt Enable register allows the user to select events that generate the Interrupt Request Output assertion. A separate ...
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Current Data Set Register, Address [0Eh]. This register indicates current selected data set for each endpoint. Table 33. Current Data Set Register [Address 0Eh Reserved Bit Position Bit Name Function 7-4 Reserved Not applicable. 3 Endpoint 3 ...
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Physical Connections These parts are offered in both a 28-pin PLCC package and a 48-pin TQFP package. The 28-pin PLCC packages are the SL811HS and SL811HS-JCT. The 48-pin TQFP packages is the SL811HST-AXC. 28-Pin PLCC Physical Connections 28-Pin PLCC Pin ...
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The diagram below illustrates a simple +3.3V voltage source. Figure 5. Sample VDD Generator +5V (USB Ohms 2N2222 Zener 3.9v, 1N52288CT- GND Package Markings (28-pin PLCC) Part Number YYWW-X.X XXXX YYWW = Date code XXXX = Product code ...
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TQFP Physical Connections 48-Pin TQFP AXC Pin Layout Figure 6. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout [ nWR nCS CM VDD1 Data+ Data- USBGnd *See Table ...
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USB Host Controller Pins Description The SL811HST-AXC is packaged in a 48-pin TQFP. The SL811HS and SL811HS-JCT packages are 28-pin PLCC’s. These devices require a 3.3 VDC power source. The 48-Pin TQFP requires an external MHz ...
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Table 35. 48/28-Pin TQFP AXC Pin Assignments and Definitions (continued) 48-Pin TQFP 28-Pin PLCC Pin Type AXC Pin No. Pin No BIDIR 34 – – – – – ...
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Package Markings (48-Pin TQFP) Part Number YYW W -X.X XXXX YYWW = Date code XXXX = Product code X.X = Silicon revision number Document 38-08008 Rev. *D SL811HS Page [+] Feedback [+] Feedback ...
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Electrical Specifications Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL811HS. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. ...
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DC Characteristics Parameter V Input Voltage LOW IL V Input Voltage HIGH (5V Tolerant I/ Output Voltage LOW ( Output Voltage HIGH ( Output Current HIGH OH I Output Current LOW OL I Input ...
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Bus Interface Timing Requirements I/O Write Cycle twr nWR twasu A0 twdsu D0-D7 twcsu nCS I/O Write Cycle to Register or Memory Buffer Parameter Description t Write pulse width WR t Chip select set-up to nWR LOW WCSU t Chip ...
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I/O Read Cycle twr nWR twasu A0 nRD twdsu D0-D7 nCS I/O Read Cycle from Register or Memory Buffer Parameter t Write pulse width WR t Read pulse width RD t Chip select set-up to nWR WCSU t A0 address ...
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DMA Write Cycle 0 Parameter Description tdack nDACK low tdwrlo nDACK to nWR low delay tdakrq nDACK low to nDRQ high delay tdwrp nWR pulse width tdhld ...
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DMA Read Cycle 0-D 7 tdaccs Parameter Description tdack nDACK low tddrdlo nDACK to nRD low delay tdckdr nDACK low to nDRQ high delay tdrdp nRD pulse ...
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Clock Timing Specifications tclk CLK thigh Parameter Description t Clock Period (48 MHz) CLK t Clock HIGH Time HIGH t Clock LOW Time LOW t Clock Rise Time RISE t Clock Fall Time FALL Clock Duty Cycle Ordering Information Part ...
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Package Diagrams (continued) 48-Lead Thin Plastic Quad Flat Pack (7x7x1.4 mm) A48 Intel is a registered trademark of Intel Corporation. Torex is a trademark of Torex Semiconductors, Ltd. SL811HS is a trademark of Cypress Semiconductor Corporation. All product and company ...
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Document History Page Document Title: SL811HS Embedded USB Host/Slave Controller Document Number: 38-08008 REV. ECN NO. Issue Date ** 110850 12/14/01 *A 112687 03/22/02 *B 381894 See ECN *C 464641 See ECN *D 749518 See ECN Document 38-08008 Rev. *D ...