SL811HS Cypress Semiconductor Corp, SL811HS Datasheet
SL811HS
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SL811HS Summary of contents
Page 1
... SL811HS supports and operates in USB full speed mode at 12 Mbps low speed mode at 1.5 Mbps. When in host mode, the SL811HS is the master and controls the USB bus and the devices that are connected to it. In peripheral mode, otherwise known as a slave device, the SL811HS operates as a variety of full- or low speed devices ...
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... SL811HS provides a DMA in- terface. This interface supports DMA READ or WRITE trans- fers to the SL811HS internal RAM buffer done through the microprocessor data bus via two control lines (nDRQ - Data Request and nDACK - Data Acknowledge), along with the nWR line and controls the data flow into the SL811HS ...
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... MHz , series, 20-pF load Cin 22 pF Note 1. CM (Clock Multiply) pin of the SL811HS must be tied to GND when 48 MHz crystal circuit or 48 MHz clock source is used. Document 38-08008 Rev. *D Typical Crystal Requirements The following are examples of ‘typical requirements.’ Note that these specifications are generally found as standard crystal ...
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... Interface Timing Requirements” on page provide control and status information for USB transactions. Any write to control register 0FH enables the SL811HS full features bit. This is an internal bit of the SL811HS that enables additional features. Table 1 shows the memory map and register mapping of the SL811HS in master/host mode ...
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... HBADD6 HBADD5 The USB-A/B Base Address is a pointer to the SL811HS memory buffer location for USB reads and writes. When transferring data OUT (Host to Device), the USB-A and USB-B Host Base Address registers can be set up before setting ARM on the USB-A or USB-B Host Control register. When using a double buffer scheme, the Host Base Address could be set up with the first buffer used for DATA0 data and the other for DATA1 data ...
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... SL811HS only has an 8-bit length; the maximum packet size for the ISO mode using the SL811HS is 255 – 16 bytes (register space). When the Host Base length register is set to zero, a Zero-Length packet is transmitted. ...
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... SL811HS Control Registers The next set of registers are the Control registers and control more of the operation of the chip instead of USB packet type of transfers. Table summary of the control registers. Table 10. SL811HS Control Registers Summary Register Name SL811H Control Register 1 Interrupt Enable Register Reserved Register ...
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... There are two cases when communicating with a low speed device. When a low speed device is connected directly to the SL811HS, bit 5 of Register 05h is set to ’1’ and bit 6 of register 0Fh, Polarity Swap, is set to ’1’ in order to change the polarity of D+ and D–. When a low speed device is connected via a HUB to SL811HS, bit 5 of Register 05h is set to ’ ...
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... Interrupt Enable Register [Address = 06h]. The SL811HS provides an Interrupt Request Output, which is activated for a number of conditions. The Interrupt Enable register allows the user to select conditions that result in an interrupt that is issued to an external CPU through the INTRQ pin. A separate Interrupt Status register reflects the reason for the interrupt. ...
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... In this mode, check this bit along with bit 5 to determine whether a device has been inserted or removed. Device Insert/Remove Detection. Bit 5 is provided to support USB cable insertion/removal for the SL811HS in host mode. This bit is set when a transition from SE0 to IDLE (device inserted) or from IDLE to SE0 (device removed) occurs on the bus. ...
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... SL811HS D+/D– Data Polarity Swap 5-0 SOF High Counter Register Note Any write to Control register 0Fh enables the SL811HS full features bit. This is an internal bit of the SL811HS that enables additional features. The USB-B register set is used when SL811HS full feature bit is enabled. ...
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... Reserved Memory Buffer 40h – FFh When in slave mode, the registers in the SL811HS are divided into two major groups. The first group contains Endpoint reg- isters that manage USB control transactions and data flow. The second group contains the USB Registers that provide the control and status information for all other operations ...
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... Endpoint Base Length [Address a = (EP# * 10h)+ (EP# * 10h)+A]. The Endpoint Base Length is the maximum packet size for IN/OUT transfers with the host. Essentially, this designates the largest packet size that is received by the SL811HS with an OUT transfer designates the size of the data packet sent to the host for IN transfers. ...
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... Endpoint Base Length register was programmed for, the overflow flag is set in the Endpoint Packet Status register and is considered a serious error EPxCNT4 EPxCNT3 unique identifier, which is the Endpoint Number. For more details about USB endpoints, refer to the USB Specification 1.1, Section 5.3.1. SL811HS Time-out Error ACK EPxCNT2 ...
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... J-K0 These two bits are set to zero on power up, see 2 DMA Dir DMA Transfer Direction. Set equal to ‘1’ for DMA READ cycles from SL811HS. Set equal to ‘0’ for DMA WRITE cycles. 1 DMA Enable Enable DMA operation when equal to ‘1’. Disable = ‘0’. DMA is initiated when DMA Count High is written ...
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... USBADD4 USBADD3 read/write interrupt, write the register with the appropriate bit set to ‘1’. Writing a ‘0’ has no effect on the status DMA Done Endpoint 3 Done Function SL811HS Interrupt [0Dh]). When a bit is set to ‘1’, the Endpoint 2 Endpoint 1 Endpoint 0 Done Done Done ...
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... Bit 5 Bit 4 Bit 3 Function only register ferred between a peripheral to the SL811HS. The count may sometimes require bits, therefore the count is repre- sented in two registers: Total Count Low and Total Count High. EP3 is only supported with DMA operation. only register DMA Total Count High Register, Address [36h]. The DMA Total Count High register contains the high order 8 bits of DMA count ...
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... Physical Connections These parts are offered in both a 28-pin PLCC package and a 48-pin TQFP package. The 28-pin PLCC packages are the SL811HS and SL811HS-JCT. The 48-pin TQFP packages is the SL811HST-AXC. 28-Pin PLCC Physical Connections 28-Pin PLCC Pin Layout *See Table 35 on page 21 for Pin and Signal Description for Pins 2 and 3 in Host Mode. Figure 4. 28-pin PLCC USB Host/Slave Controller — ...
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... The diagram below illustrates a simple +3.3V voltage source. Figure 5. Sample VDD Generator +5V (USB Ohms Zener 3.9v, 1N52288CT- GND Package Markings (28-pin PLCC) Part Number YYWW-X.X XXXX YYWW = Date code XXXX = Product code X.X = Silicon revision number Document 38-08008 Rev. *D 2N2222 +3.3 V (VDD) Sample VDD Generator SL811HS Page ...
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... Pin and Signal Description for Pins 43 and 44 in Host Mode. 48-Pin TQFP Mechanical Dimensions Note 4. NC. Indicates No Connection. NC Pins must be left unconnected. Document 38-08008 Rev. *D nRD nDACK* NC VDD [4] nDRQ M/S 48 48-Pin TQFP 12 nRST GND NC Clk/X1 NC VDD D0 X2 INTRQ SL811HS GND Page ...
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... USB Host Controller Pins Description The SL811HST-AXC is packaged in a 48-pin TQFP. The SL811HS and SL811HS-JCT packages are 28-pin PLCC’s. These devices require a 3.3 VDC power source. The 48-Pin TQFP requires an external MHz crystal or clock. Table 35. 48/28-Pin TQFP AXC Pin Assignments and Definitions ...
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... DMA Request. An active LOW output used with an external DMA controller. nDRQ and nDACK form the handshake for DMA data transfers. In host mode, leave the pin unconnected. nRD Read Strobe Input. An active LOW input used with nCS to read registers/data memory connection connection connection. SL811HS Page ...
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... Package Markings (48-Pin TQFP) Part Number YYW W -X.X XXXX YYWW = Date code XXXX = Product code X.X = Silicon revision number Document 38-08008 Rev. *D SL811HS Page ...
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... Electrical Specifications Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL811HS. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Description Storage Temperature Voltage on any pin with respect to ground ...
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... Clock, PLL disabled, and Suspend set. For absolute minimum current consumption, ensure that all inputs to the device are at CCsus2 static logic level. 16. All typical values are V = 3.3V and T DD AMB 17. Z impedance values includes an external resistor of 24 Ohms ± 1% (SL811HS revision 1.2 requires external resistor values of 33 Ohms ±1%). USBX Document 38-08008 Rev. *D Description = 4 mA –4 mA inc USB @FS ) Suspend w/Clk & ...
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... Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170 ns minimum. Document 38-08008 Rev. *D twr twahld twdhld Register or Memory Address twshld Min SL811HS twrhigh twdsu twdhld DATA Tcscs See Note. Typ. Max. Page ...
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... Note nCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is 170 ns minimum. Document 38-08008 Rev. *D twr twahld trdp twdhld Register or Memory Address trcsu I/O Read Cycle from Register or Memory Buffer Description SL811HS twrrdl tracc trdhld DATA trshld Tcscs *Note Min. Typ. Max ...
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... Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the next nDRQ is not inserted. Document 38-08008 Rev. *D tdakrq tdack tdw rlo tdsu DMA Write Cycle SL811 TIM IN G Description Min 150 ns SL811HS tackrq tdw rp tdhld tackw rh Typ. Page Max. ...
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... HIGH to nRD or nWR active IOACT Note Clock is 48 MHz nominal. Document 38-08008 Rev. *D tdckdr tdack tddrdlo tdrdp SL811 DMA Read Cycle Timing S L 811 Min. 100 150 ns treset tioact Reset Timing Description Min. 16 clocks 16 clocks SL811HS tdakrq tdhld Typ. Typ. Page Max. Max. ...
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... PLCC 28-pin Lead free 48-pin Lead free 28-Lead Plastic Leaded Chip Carrier J64 SEATING PLANE 0.045 0.055 19 0.026 0.032 18 0.450 0.458 0.485 0.495 SL811HS trise Typ. Max. 20 5.0 ns 5.0 ns 55% – – – DIMENSIONS IN INCHES MIN. MAX. 0.013 0.021 0.390 ...
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... Thin Plastic Quad Flat Pack (7x7x1.4 mm) A48 Intel is a registered trademark of Intel Corporation. Torex is a trademark of Torex Semiconductors, Ltd. SL811HS is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. ...
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... Implemented the new template. Changed Figure 4. Labels on pins 2 and 3 were swapped; this has been corrected. Combined the 48-pin TQFP AXC Pin Assignment and Definition table with the 28-pin PLCC Pin Assignment and Definition table. Removed all instances of SL811HST-AC. Corrected the variables. Removed references to the obsolete SL11H. SL811HS Ordering Information ...