ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 48

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 38. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
1
2
Table 39. 10/100 Ethernet MAC Controller Timing: MII Station Management
1
Parameter
t
t
t
t
Parameter
t
t
t
t
MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
ECOLH
ECOLL
ECRSH
ECRSL
MDIOS
MDCIH
MDCOV
MDCOH
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
of the system clock SCLK. MDIO is a bidirectional data line.
ERxCLK
ERxD3-0
ERxDV
ERxER
1, 2
1
ETxD3-0
ETxEN
MII TxCLK
COL Pulse Width High
COL Pulse Width Low
CRS Pulse Width High
CRS Pulse Width Low
MDIO Input Valid to MDC Rising Edge (Setup)
MDC Rising Edge to MDIO Input Invalid (Hold)
MDC Falling Edge to MDIO Output Valid
MDC Falling Edge to MDIO Output Invalid (Hold)
t
ERXCLKIS
Figure 30. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Figure 29. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
t
ETXCLKOH
t
ERXCLKIH
t
ETXCLKW
t
ETXCLKOV
t
ERXCLKW
Rev. B | Page 48 of 68 | July 2006
t
ETXCLK
t
ERXCLK
Min
t
t
t
t
t
t
Min
10
10
25
–1
ETxCLK
ERxCLK
ETxCLK
ERxCLK
ETxCLK
ETxCLK
1.5
1.5
1.5
1.5
1.5
1.5
Max
Max
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns