ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 46

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF534/ADSP-BF536/ADSP-BF537
JTAG Test and Emulation Port Timing
Table 33
Table 33. JTAG Port Timing
1
2
3
Parameter
Timing Parameters
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = DATA15–0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH15–0, MDIO, TCK, TD1, TMS, TRST, RESET,
50 MHz maximum
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
NMI, BMODE2–0.
DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTX0, TD0, EMU, XTAL, VROUT.
and
TCK
TMS
TDO
SYSTEM
OUTPUTS
Figure 28
INPUTS
TDI
SYSTEM
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay From TCK Low
System Outputs Delay After TCK Low
describe JTAG port operations.
2
(Measured in TCK Cycles)
t
DSYS
t
DTDO
t
SSYS
t
STAP
Rev. B | Page 46 of 68 | July 2006
1
t
TCK
3
1
Figure 28. JTAG Port Timing
t
HSYS
t
HTAP
Min
20
4
4
4
5
4
0
Max
10
12
Unit
TCK
ns
ns
ns
ns
ns
ns
ns