ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 15

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Because of the default 10x PLL multiplier, providing a 50 MHz
CLKIN exceeds the recommended operating conditions of the
lower speed grades. Because of this restriction, a 50 MHz RMII
PHY cannot be clocked directly from the CLKBUF pin. Either
provide a separate 50 MHz clock source, or use an RMII PHY
with 25 MHz clock input options. The CLKBUF output is active
by default and can be disabled using the VR_CTL register for
power savings.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 0.5 to 64 multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 10 , but it can be modi-
fied by a software instruction sequence in the PLL_CTL register.
On-the-fly CCLK and SCLK frequency changes can be effected
by simply writing to the PLL_DIV register. Whereas the maxi-
mum allowed CCLK and SCLK rates depend on the applied
voltages V
up to the frequency specified by the part’s speed grade. The
CLKOUT pin reflects the SCLK frequency to the off-chip world.
It belongs to the SDRAM interface, but it functions as reference
signal in other timing specifications as well. While active by
default, it can be disabled using the EBIU_SDGCTL and
EBIU_AMGCTL registers.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Table 6
CLKOUT
CLKBUF
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
DDINT
illustrates typical system clock ratios.
and V
Figure 6. External Crystal Connections
EN
EN
DDEXT
CLKIN
18pF*
BLACKFIN
Figure
, the VCO is always permitted to run
330 *
TO PLL CIRCUITRY
7, the core clock (CCLK) and
XTAL
18pF*
FOR OVERTONE
OPERATION ONLY:
Rev. B | Page 15 of 68 | July 2006
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
Table 6. Example System Clock Ratios
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
fast core frequency modifications.
Table 7. Core Clock Ratios
The maximum CCLK frequency not only depends on the part’s
speed grade (see
the applied V
The maximal system clock rate (SCLK) depends on the chip
package and the applied V
ADSP-BF534/ADSP-BF536/ADSP-BF537
Signal Name
SSEL3–0
0001
0110
1010
Signal Name
CSEL1–0
00
01
10
11
CLKIN
REQUIRES PLL SEQUENCING
7. This programmable core clock capability is useful for
“FINE” ADJUSTMENT
DDINT
0.5
Figure 7. Frequency Modification Methods
PLL
Ordering Guide on Page
Divider Ratio
VCO/SCLK
1:1
6:1
10:1
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
- 64
voltage. See
SCLK CCLK
SCLK
DDEXT
133MHz
VCO
Table 12
voltage (see
“COURSE” ADJUSTMENT
Example Frequency Ratios
(MHz)
VCO
300
300
500
200
Example Frequency Ratios
(MHz)
VCO
100
300
500
SCLK
1, 2, 4, 8
1 TO 15
ON THE FLY
and
. The SSEL value can be
66), it also depends on
Table 13
Table
CCLK
SCLK
SCLK
100
50
50
CCLK
300
150
125
25
16).
for details.