ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 19

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

PIN DESCRIPTIONS
ADSP-BF534/ADSP-BF536/ADSP-BF537 processor’s pin defi-
nitions are listed in
function and reduce package size and pin count, some pins have
dual, multiplexed functions. In cases where pin function is
reconfigurable, the default state is shown in plain text, while the
alternate function is shown in italics. Pins shown with an aster-
isk after their name (*) offer high source/high sink current
capabilities.
Table 9. Pin Descriptions
Pin Name
Memory Interface
Asynchronous Memory Control
Synchronous Memory Control
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
ARDY
AOE
ARE
AWE
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
AMS3–0
Table
9. In order to maintain maximum
Type Function
O
I/O
O
I
O
O
O
I
O
O
O
O
O
O
O
O
O
O
Address Bus for Async Access
Data Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access A
Bus Request
Bus Grant
Bus Grant Hang
Bank Select
Output Enable
Read Enable
Write Enable
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output
A10 Pin
Bank Select
Hardware Ready Control
Rev. B | Page 19 of 68 | July 2006
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface and the
buffered XTAL output pin (CLKBUF). On the external memory
interface, the control and address lines are driven high during
reset unless the BR pin is asserted.
All I/O pins have their input buffers disabled with the exception
of the pins noted in the data sheet that need pull-ups or pull-
downs if unused.
The SDA (serial data) and SCL (serial clock) pins are open drain
and therefore require a pull-up resistor. Consult version 2.1 of
the I
ADSP-BF534/ADSP-BF536/ADSP-BF537
2
C specification for the proper resistor value.
Driver
Type
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
1
Pull-Up/Pull-Down
This pin should be pulled high when
not used