ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 37

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Table 27. External Late Frame Sync
1
2
Parameter
Switching Characteristics
t
t
MCE = 1, TFS enable and TFS valid follow t
If external RFS/TFS setup to RSCLK/TSCLK > t
DDTLFSE
DTENLFS
TFS (“LATE,” EXT.)
RSCLK
TSCLK
TFS (“LATE,” INT.)
TSCLK (EXT.)
DATA RECEIVE - INTERNAL CLOCK
TSCLK (INT.)
DATA TRANSMIT - INTERNAL CLOCK
RFS
DR
TFS
DT
DT
DT
t
HOFSE
t
HOFSI
t
HDTI
DRIVE
DRIVE
EDGE
EDGE
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0
Data Enable from Late FS or MCE = 1, MFD = 0
t
DFSE
t
t
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DFSI
DDTI
DRIVE
EDGE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
t
t
SCLKIW
SCLKIW
DDTENFS
t
t
SFSI
t
SDRI
SFSI
t
DDTENI
SCLKE
t
DDTENE
and t
/2, then t
SAMPLE
SAMPLE
EDGE
EDGE
DDTLFS
DDTE/I
.
Rev. B | Page 37 of 68 | July 2006
and t
t
t
HDRI
t
HFSI
HFSI
DTENE/I
Figure 19. Serial Ports
apply, otherwise t
1, 2
TSCLK/RSCLK
TSCLK/RSCLK
ADSP-BF534/ADSP-BF536/ADSP-BF537
RSCLK
TSCLK
RFS
TFS
DATA RECEIVE - EXTERNAL CLOCK
DR
DT
DDTLFSE
DATA TRANSMIT - EXTERNAL CLOCK
t
t
HOFSE
HOFSE
t
HDTE
and t
DRIVE
DRIVE
EDGE
EDGE
DTENLFS
DRIVE
DRIVE
EDGE
EDGE
t
t
1, 2
DFSE
DFSE
t
DDTE
apply.
t
t
SCLKEW
SCLKEW
t
Min
0
DDTTI
t
t
t
SFSE
SDRE
SFSE
t
DDTTE
SAMPLE
SAMPLE
EDGE
EDGE
Max
10.0
t
t
t
HDRE
HFSE
HFSE
Unit
ns
ns