ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

These modes support ADC/DAC connections, as well as video
communication with hardware signalling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
DYNAMIC POWER MANAGEMENT
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide five operating modes, each with a different performance
and power profile. In addition, dynamic power management
provides the control functions to dynamically alter the proces-
sor core supply voltage, further reducing power dissipation.
Control of clocking to each of the peripherals also reduces
power consumption. See
settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured
L1 memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Table 4. Power Settings
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wakeup causes the processor
to sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
Mode
Full On
Active
Sleep
Deep Sleep
Hibernate
PLL
Enabled
Enabled/
Disabled
Enabled
Disabled
Disabled
Table 4
PLL
Bypassed
No
Yes
—
—
—
for a summary of the power
Core
Clock
(CCLK)
Enabled
Enabled
Disabled
Disabled
Disabled
System
Clock
(SCLK)
Enabled
Enabled
Enabled
Disabled
Disabled
Rev. B | Page 13 of 68 | July 2006
Internal
Power
(VDDINT)
On
On
On
On
Off
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the proces-
sor to transition to the active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the full-
on mode.
Hibernate Operating Mode—Maximum Static Power
Savings
The hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all of the synchronous peripherals (SCLK). The internal volt-
age regulator for the processor can be shut off by writing b#00 to
the FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (V
preserve the processor state, prior to removing power, any criti-
cal information stored internally (memory contents, register
contents, etc.) must be written to a non volatile storage device.
Since V
three-state, unless otherwise specified. This allows other devices
that are connected to the processor to still have power applied
without drawing unwanted current.
The Ethernet or CAN modules can wake up the internal supply
regulator. The regulator can also be woken up by a real-time
clock wakeup event or by asserting the RESET pin, both of
which initiate the hardware reset sequence.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hiber-
nate state. State variables may be held in external SRAM or
SDRAM. The CKELOW bit in the VR_CTL register controls
whether SDRAM operates in self-refresh mode which allows it
to retain its content while the processor is in reset.
Power Savings
As shown in
power domains which maximizes flexibility, while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
ADSP-BF534/ADSP-BF536/ADSP-BF537
DDINT
DDEXT
) to 0 V to provide the greatest power savings. To
is still supplied in this mode, all of the external pins
Table
5, the processors support three different