CY7C1480BV33_11 CYPRESS [Cypress Semiconductor], CY7C1480BV33_11 Datasheet - Page 28

• Manufacturer Part Number: CY7C1480BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Figure 5
Document Number: 001-15145 Rev. *F
Notes
21. On this diagram, when CE is LOW: CE
22. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
23. GW is HIGH.
Data Out (Q)
Data In (D)
ADDRESS
ADSP
ADSC
BWE,
BW
ADV
CLK
OE
CE
X
shows read-write cycle timing.
A1
High-Z
High-Z
t ADS
t CES
t AS
A2
t ADH
t CEH
t CH
t AH
Back-to-Back READs
t CYC
t CLZ
Q(A1)
t CL
t CO
(continued)
1
is LOW, CE
Q(A2)
t OEHZ
[21, 22, 23]
2
Figure 5. Read/Write Cycle Timing
is HIGH, and CE
t WES
t DS
D(A3)
Single WRITE
A3
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
t DH
t WEH
DON’T CARE
A4
3
is LOW. When CE is HIGH: CE
t OELZ
UNDEFINED
Q(A4)
BURST READ
Q(A4+1)
1
is HIGH, CE
Q(A4+2)
2
is LOW, or CE
Q(A4+3)
3
is HIGH.
D(A5)
A5
Back-to-Back
WRITEs
Page 28 of 36
D(A6)
A6
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