CY7C1480BV33_11 CYPRESS [Cypress Semiconductor], CY7C1480BV33_11 Datasheet - Page 27

• Manufacturer Part Number: CY7C1480BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Figure 4
Document Number: 001-15145 Rev. *F
Notes
Data Out (Q)
19. On this diagram, when CE is LOW: CE
20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BW
Data In (D)
ADDRESS
ADSP
ADSC
BWE,
ADV
BW
CLK
GW
OE
CE
X
shows write cycle timing.
BURST READ
High-Z
t ADS
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t CL
t DS
Single WRITE
D(A1)
(continued)
t ADH
t DH
[19, 20]
1
is LOW, CE
A2
2
is HIGH, and CE
D(A2)
Figure 4. Write Cycle Timing
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
DON’T CARE
t WES
D(A2 + 1)
3
is LOW. When CE is HIGH: CE
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
ADV suspends burst
X
LOW.
D(A2 + 2)
ADSC extends burst
1
is HIGH, CE
D(A2 + 3)
t ADS
2
is LOW, or CE
A3
D(A3)
t ADH
t
ADVS
t WES
Extended BURST WRITE
D(A3 + 1)
3
t
is HIGH.
t WEH
ADVH
D(A3 + 2)
Page 27 of 36
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