CY7C1480BV33_11 CYPRESS [Cypress Semiconductor], CY7C1480BV33_11 Datasheet - Page 25

• Manufacturer Part Number: CY7C1480BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Over the Operating Range
Document Number: 001-15145 Rev. *F
Notes
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
14. Timing reference level is 1.5 V when V
17. t
18. At any supplied voltage and temperature, t
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
15. Test conditions shown in (a) of
16. This part has an internal voltage regulator; t
19. This parameter is sampled and not 100% tested.
be initiated.
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high-Z before low-Z under the same system conditions.
CHZ
Parameter
, t
CLZ
,t
OELZ
, and t
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low-Z
Clock to high-Z
OE LOW to output valid
OE LOW to output low-Z
OE HIGH to output high-Z
Address setup before CLK rise
ADSC, ADSP setup before CLK rise
ADV setup before CLK rise
GW, BWE, BW
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
GW, BWE, BW
Data input hold after CLK rise
Chip enable hold after CLK rise
OEHZ
DD
(typical) to the first access
are specified with AC test conditions shown in part (b) of
[14, 15]
Figure 4 on page 24
DDQ
[17, 18, 19]
X
X
[17, 18, 19]
OEHZ
= 3.3 V and is 1.25 V when V
POWER
setup before CLK rise
hold after CLK rise
Description
is less than t
is the time that the power needs to be supplied above V
unless otherwise noted.
[17, 18, 19]
[17, 18, 19]
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
OELZ
[16]
and t
CHZ
DDQ
is less than t
= 2.5 V.
Figure 4 on page
Min
1.3
1.3
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
CLZ
4.0
2.0
2.0
1.4
1.4
0.4
1
–
–
–
0
–
250 MHz
to eliminate bus contention between SRAMs when sharing the same data
Max
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
24. Transition is measured ±200 mV from steady-state voltage.
DD
(minimum) initially before a read or write operation can
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
0
–
200 MHz
Max
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
1.5
1.5
0.5
6.0
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
0
–
167 MHz
Max
3.4
3.4
3.4
3.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 25 of 36
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback