CY7C1480BV33_11 CYPRESS [Cypress Semiconductor], CY7C1480BV33_11 Datasheet - Page 19

• Manufacturer Part Number: CY7C1480BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Identification Register Definitions
Scan Register Sizes
Identification Codes
Document Number: 001-15145 Rev. *F
Revision number (31:29)
Device depth (28:24)
Architecture/Memory type(23:18)
Bus width/density(17:12)
Cypress JEDEC ID Code (11:1)
ID register presence indicator (0)
Instruction
Bypass
ID
Boundary scan order – 165-ball FBGA
Boundary scan order – 209-ball BGA
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction Field
Instruction
Register Name
CY7C1480BV33
00000110100
(2 M × 36)
000000
100100
01011
000
1
Code
000
001
010
011
100
101
110
111
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Captures the I/O ring contents.
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operations.
CY7C1482BV33
00000110100
(4 M × 18)
Bit Size (× 36)
000000
010100
01011
000
1
32
73
3
1
–
CY7C1486BV33
00000110100
(1 M × 72)
000000
110100
01011
000
1
Bit Size (× 18)
Description
32
54
3
1
–
Reserved for internal use
Defines width and density
Enables unique identification of SRAM
Indicates the presence of an ID register
Describes the version number
Defines memory type and architecture
vendor
Description
Bit Size (× 72)
112
32
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