CY7C1480BV33_11 CYPRESS [Cypress Semiconductor], CY7C1480BV33_11 Datasheet - Page 18

• Manufacturer Part Number: CY7C1480BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

TAP AC Switching Characteristics
Over the Operating Range
TAP Timing
Document Number: 001-15145 Rev. *F
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
Notes
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
9. t
10. Test conditions are specified using the load in TAP AC Test Conditions. t
Parameter
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS setup to TCK clock rise
TDI setup to TCK Clock rise
Capture setup to TCK rise
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
Test M ode Select
Test Data-Out
Test Data-In
[9, 10]
Test Clock
(TDO)
(TM S)
(TCK )
(TDI)
1
Description
t TM SS
t TDIS
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
2
Figure 3. TAP Timing
t TM SH
t TDIH
t TH
DON’T CA RE
R
/t
t
TL
F
= 1 ns.
3
t CY C
UNDEFINED
4
t TDOX
t TDOV
5
Min
6
50
20
20
–
–
0
5
5
5
5
5
5
Max
20
10
–
–
–
–
–
–
–
–
–
–
Page 18 of 36
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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