CY7C1480BV33-250BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV33-250BZXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1480BV33-250BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Truth Table
The truth table for CY7C1480BV33 and CY7C1482BV33 follows.
Document Number: 001-15145 Rev. *H
Notes
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Sleep mode, power-down
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Read cycle, begin burst
Read cycle, begin burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Write cycle, continue burst
Write cycle, continue burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Write cycle, suspend burst
Write cycle, suspend burst
2. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tri-state. OE is a do not care for
the remainder of the write cycle.
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Operation
Address Used CE
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
H
X
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
1
CE
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
2
[2, 3, 4, 5, 6]
CE
H
H
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
3
ZZ ADSP ADSC ADV WRITE OE CLK
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
X
. Writes may occur only on subsequent clocks after the
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
L
L
X
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
CY7C1480BV33
CY7C1482BV33
X
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
L–H Tri-state
L–H Tri-state
L–H Tri-state
L–H Tri-state
L–H Tri-state
L–H
L–H Tri-state
L–H
L–H
L–H Tri-state
L–H
L–H Tri-state
L–H
L–H Tri-state
L–H
L–H
L–H
L–H Tri-state
L–H
L–H Tri-state
L–H
L–H
X
Page 9 of 33
Tri-state
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D