CY7C1480BV33-250BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV33-250BZXC Datasheet - Page 23

• Manufacturer Part Number: CY7C1480BV33-250BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Over the Operating Range
Document Number: 001-15145 Rev. *H
Notes
Parameter
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
15. Timing reference level is 1.5 V when V
16. Test conditions shown in (a) of
17. This part has an internal voltage regulator; t
18. t
19. At any supplied voltage and temperature, t
20. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
initiated.
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z before low Z under the same system conditions.
CHZ
, t
CLZ
,t
[15, 16]
OELZ
, and t
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address setup before CLK rise
ADSC, ADSP setup before CLK rise
ADV setup before CLK rise
GW, BWE, BW
rise
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
GW, BWE, BW
Data input hold after CLK rise
Chip enable hold after CLK rise
OEHZ
DD
(typical) to the first access
are specified with AC test conditions shown in part (b) of
Figure 4 on page 22
Description
DDQ
[18, 19, 20]
X
X
[18, 19, 20]
hold after CLK rise
setup before CLK
OEHZ
POWER
= 3.3 V and is 1.25 V when V
is less than t
is the time that the power needs to be supplied above V
unless otherwise noted.
[18, 19, 20]
[18, 19, 20]
[17]
OELZ
and t
CHZ
DDQ
Min
4.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
is less than t
1
–
–
–
0
–
250 MHz
= 2.5 V.
Figure 4 on page
CLZ
Max
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
to eliminate bus contention between SRAMs when sharing the same data
22. Transition is measured ±200 mV from steady-state voltage.
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
0
–
DD(minimum)
200 MHz
Max
3.0
3.0
3.0
3.0
initially before a read or write operation can be
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY7C1480BV33
CY7C1482BV33
Min
6.0
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
0
–
167 MHz
Max
3.4
3.4
3.4
3.4
Page 23 of 33
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns