CY7C1480BV33-250BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV33-250BZXC Datasheet

CY7C1480BV33-250BZXC

Manufacturer Part Number

CY7C1480BV33-250BZXC

Description

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C1480BV33-250BZXC.pdf (33 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1480BV33-250BZXC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Current page: 1 of 33
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72-Mbit (2 M × 36/4 M × 18) Pipelined Sync SRAM

Features

■

Selection Guide

Cypress Semiconductor Corporation

Document Number: 001-15145 Rev. *H

Maximum access time

Maximum operating current

Maximum CMOS standby current

Supports bus operation up to 250 MHz

Available speed grades are 250, 200, and 167 MHz

Registered inputs and outputs for pipelined operation

3.3 V core power supply

2.5 V/3.3 V I/O operation

Fast clock-to-output times

❐

Provide high performance 3-1-1-1 access rate

User selectable burst counter supporting Intel

interleaved or linear burst sequences

Separate processor and controller address strobes

Synchronous self timed writes

Asynchronous output enable

Single cycle chip deselect

CY7C1480BV33 available in JEDEC-standard Pb-free 100-pin

thin quad flat pack (TQFP), Pb-free and non Pb-free 165-ball

fine-pitch ball grid array (FBGA) package. CY7C1482BV33

available in non Pb-free 165-ball fine-pitch ball grid array

(FBGA) package

IEEE 1149.1 JTAG-compatible boundary scan

“ZZ” sleep mode option

3.0 ns (for 250 MHz device)

Description

•

198 Champion Court

Pentium

Functional Description

The CY7C1480BV33 and CY7C1482BV33 SRAM integrates

2 M × 36/4 M × 18 SRAM cells with advanced synchronous

peripheral circuitry and a 2-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE

Enables (CE

ADV), Write Enables (BW

Asynchronous inputs include the Output Enable (OE) and the ZZ

pin.

Addresses and chip enables are registered at the rising edge of

the clock when either address strobe processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent burst

addresses may be internally generated as controlled by the

advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see sections

Table on page 9

two or four bytes wide as controlled by the byte write control

inputs. GW when active LOW causes all bytes to be written.

The CY7C1480BV33 and CY7C1482BV33 operates from a

+3.3 V core power supply while all outputs may operate with

either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC

standard

recommendations, refer to the Cypress application note

“SRAM System Guidelines”.

72-Mbit (2 M × 36/4 M × 18)

•

San Jose

JESD8-5

and CE

for further details). Write cycles can be one to

Pipelined Sync SRAM

250 MHz

500

120

3.0

), Burst Control inputs (ADSC, ADSP, and

CA 95134-1709

compatible.

Pin Definitions on page 6

, and BWE), and Global Write (GW).

200 MHz

500

120

3.0

CY7C1480BV33

CY7C1482BV33

), depth-expansion Chip

For

Revised May 25, 2012

•

167 MHz

best

450

120

3.4

408-943-2600

and

practices

AN1064

Unit

Truth

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