CY7C1480BV33-250BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV33-250BZXC Datasheet - Page 26

• Manufacturer Part Number: CY7C1480BV33-250BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Document Number: 001-15145 Rev. *H
Notes
24. On this diagram, when CE is LOW: CE
25. The data bus (Q) remains in high Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
26. GW is HIGH.
Data Out (Q)
Data In (D)
ADDRESS
ADSP
ADSC
BWE,
BW
ADV
CLK
OE
CE
X
A1
High-Z
High-Z
t ADS
t CES
t AS
A2
t ADH
t CEH
t CH
t AH
Back-to-Back READs
t CYC
t CLZ
Q(A1)
t CL
(continued)
t CO
1
is LOW, CE
Q(A2)
t OEHZ
Figure 5. Read/Write Cycle Timing
2
is HIGH, and CE
t WES
t DS
D(A3)
Single WRITE
A3
t DH
t WEH
DON’T CARE
3
A4
is LOW. When CE is HIGH: CE
t OELZ
UNDEFINED
Q(A4)
[24, 25, 26]
BURST READ
1
Q(A4+1)
is HIGH, CE
Q(A4+2)
2
is LOW, or CE
Q(A4+3)
CY7C1480BV33
CY7C1482BV33
3
is HIGH.
D(A5)
A5
Back-to-Back
WRITEs
Page 26 of 33
D(A6)
A6