CY7C1480BV33-250AXI Cypress Semiconductor Corporation., CY7C1480BV33-250AXI Datasheet

CY7C1480BV33-250AXI

Manufacturer Part Number

CY7C1480BV33-250AXI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1480BV33-250AXI.pdf (34 pages)

2.CY7C1480BV33-250AXI.pdf (34 pages)

Specifications of CY7C1480BV33-250AXI

Package

QFP

Date_code

09+

Current page: 1 of 34
Download datasheet (970Kb)

Features

■

Selection Guide

Cypress Semiconductor Corporation

Document #: 001-15145 Rev. *A

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Supports bus operation up to 250 MHz

Available speed grades are 250, 200, and 167 MHz

Registered inputs and outputs for pipelined operation

3.3V core power supply

2.5V/3.3V IO operation

Fast clock-to-output times

❐

Provide high performance 3-1-1-1 access rate

User selectable burst counter supporting Intel

Pentium

Separate processor and controller address strobes

Synchronous self timed writes

Asynchronous output enable

Single cycle chip deselect

CY7C1480BV33, CY7C1482BV33 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non Pb-free 165-ball FBGA package. CY7C1486BV33

available in Pb-free and non-Pb-free 209-ball FBGA package

IEEE 1149.1 JTAG-Compatible Boundary Scan

“ZZ” Sleep Mode option

3.0 ns (for 250 MHz device)

interleaved or linear burst sequences

Description

•

198 Champion Court

72-Mbit (2M x 36/4M x 18/1M x 72)

Functional Description

The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33

SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with

advanced synchronous peripheral circuitry and a 2-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE

Chip Enables (CE

ADSP, and ADV), Write Enables (BW

Write (GW). Asynchronous inputs include the Output Enable

(OE) and the ZZ pin.

Addresses and chip enables are registered at the rising edge of

the clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent burst

addresses may be internally generated as controlled by the

Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see sections

Table

two or four bytes wide as controlled by the byte write control

inputs. GW when active LOW causes all bytes to be written.

The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33

operates from a +3.3V core power supply while all outputs may

operate with either a +2.5 or +3.3V supply. All inputs and outputs

are JEDEC standard JESD8-5 compatible. For best practices

recommendations, refer to the Cypress application note

“SRAM System Guidelines”.

250 MHz

500

120

3.0

on page 10 for further details). Write cycles can be one to

•

CY7C1482BV33, CY7C1486BV33

San Jose

Pipelined Sync SRAM

200 MHz

500

120

and CE

3.0

CA 95134-1709

Pin Definitions

), Burst Control inputs (ADSC,

167 MHz

CY7C1480BV33

450

120

3.4

Revised March 05, 2008

, and BWE), and Global

on page 7 and

•

), depth-expansion

408-943-2600

Unit

AN1064

Truth

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