CY7C1480BV33-250BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV33-250BZXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1480BV33-250BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Document Number: 001-15145 Rev. *H
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs, DQPs
V
V
V
V
Note
Pin Name
1. Applicable for TQFP package. For BGA package V
0
DD
SS
SSQ
DDQ
, A
1
2
3
A
C
,BW
,BW
1
[1]
, A
B
D
,
Asynchronous
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
I/O Ground Ground for the I/O circuitry.
I/O power
Ground
supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
I/O-
I/O
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
if ADSP or ADSC is active LOW, and CE
counter.
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
is conducted (all bytes are written, regardless of the values on BW
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW during a burst operation.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
new external address is loaded.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “Sleep” input, active HIGH. When asserted HIGH, places the device in a non-time-critical “sleep”
condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
pin has an internal pull-down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP
in a tri-state condition.
Ground for the core of the device.
Power supply for the I/O circuitry.
2
3
3
to select or deselect the device. CE
to select or deselect the device. ADSP is ignored if CE
to select or deselect the device. CE
SS
1
serves as ground for the core and the I/O circuitry.
is deasserted HIGH.
1
, CE
3
2
Description
2
is sampled only when a new external address is loaded.
is sampled only when a new external address is loaded.
, and CE
3
are sampled active. A1:A0 are fed to the 2-bit
1
is HIGH. CE
X
and BWE).
CY7C1480BV33
CY7C1482BV33
1
is sampled only when a
X
Page 6 of 33
are placed
2
1
1