CY7C1480BV33-250BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV33-250BZXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1480BV33-250BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE
appropriate combination of the Write inputs (GW, BWE, and
BW
ADSC-triggered Write accesses require a single clock cycle to
complete. The address presented to A is loaded into the address
register and the address advancement logic when being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation remain unaltered. A synchronous self-timed Write
mechanism is provided to simplify the Write operations.
Because the CY7C1480BV33 and CY7C1482BV33 are a
common I/O device, the Output Enable (OE) must be deasserted
HIGH before presenting data to the DQs inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a Write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1480BV33 and CY7C1482BV33 provide a 2-bit
wraparound counter, fed by A1:A0, that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
ZZ Mode Electrical Characteristics
Document Number: 001-15145 Rev. *H
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
X
) are asserted active to conduct a Write to the desired byte.
1
, CE
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to Sleep current
ZZ Inactive to exit Sleep current This parameter is sampled
2
, CE
3
Description
are all asserted active, and (4) the
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
DD
DD
– 0.2 V
– 0.2 V
Test Conditions
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
When in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid, and the completion of the operation is not guaranteed. The
device must be deselected before entering the “sleep” mode.
CE
duration of t
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table
(MODE = GND)
Address
Address
1
, CE
A1:A0
A1:A0
First
First
00
01
10
11
00
01
10
11
2
, CE
ZZREC
3
, ADSP, and ADSC must remain inactive for the
Address
Address
after the ZZ input returns LOW.
Second
Second
A1:A0
A1:A0
01
00
11
10
01
10
11
00
DD
)
Address
Address
A1:A0
A1:A0
Third
Third
2t
Min
10
11
00
01
10
11
00
01
CYC
CY7C1480BV33
CY7C1482BV33
–
–
–
0
2t
2t
Max
Address
Address
120
Fourth
Fourth
CYC
CYC
A1:A0
A1:A0
–
–
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11
10
01
00
11
00
01
10
Unit
mA
ns
ns
ns
ns