MT42C4256C-10/883C AUSTIN [Austin Semiconductor], MT42C4256C-10/883C Datasheet - Page 45

• Manufacturer Part Number: MT42C4256C-10/883C
• Description: 256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM
• Manufacturer: AUSTIN [Austin Semiconductor]

NOTES:
NOTE Q: In order to achieve proper split-register operation, a normal read transfer should be performed before the first split-register transfer cycle.
This is necessary to initialize the data register and the starting tap location. First serial access can then begin either after the normal read-transfer
cycle (CASE I), during the first split-register cycle (CASE II), or even after the first split-register transfer cycle (CASE III). There is no minimum
requirement of SC clock between the normal read-transfer cycle and the first split-register cycle.
NOTE R: A split register transfer into the inactive half is not allowed until t
of the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\ of the split-register transfer cycle into the inactive half. After t
is met, the split-register transfer into the inactive half must also satisfy the t
rising edge of RAS\ of the split-register transfer cycle into the inactive half and the rising edge of the serial clock of the last bit (bit 255 or 511). There
is a minimum requirement of one rising edge of SC clock between two split-register transfer cycles.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
FIGURE 35: Split-Register-Transfer Operating Sequence
Austin Semiconductor, Inc.
45
d(MSRL)
d(RHMS)
is met. t
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
requirement. t
d(MSRL)
is the minimum delay time between the rising edge
d(RHMS)
is the minimum delay time between the
SMJ44C251B
MT42C4256
VRAM
VRAM
VRAM
VRAM
VRAM
d(MSRL)