MT42C4256C-10/883C AUSTIN [Austin Semiconductor], MT42C4256C-10/883C Datasheet - Page 12

• Manufacturer Part Number: MT42C4256C-10/883C
• Description: 256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM
• Manufacturer: AUSTIN [Austin Semiconductor]

TRANSFER-OPERATION FUNCTIONS
LEGEND:
H = High
L = Low
X = Don’t Care
WRITE TRANSFER
transfer the entire content of SAM to the selected row in the
DRAM. To invoke a write-transfer cycle, W\ must be low when
RAS\ falls. There are three possible write-transfer operations:
normal-write transfer, alternate-write transfer, and pseudo-write
transfer. All write-transfer cycles switch the serial port to the
serial-in mode.
NORMAL-WRITE TRANSFER
(SAM-to-DRAM transfer)
serial-data register to a selected row in the memory array. TRG\,
W\, and SE\ are brought low and latched at the falling edge of
RAS\. Nine row-address bits (A0–A8) are also latched at the
falling edge of RAS\ to select one of the 512 rows available as
the destination of the data transfer. The nine column-address
bits (A0–A8) are latched at the falling edge of CAS\ to select
one of the 512 tap points in SAM that are available for the next
serial input.
serial-input operation must be suspended after a minimum
delay of t
t
ALTERNATE-WRITE TRANSFER
(refer to Figure 30)
of RAS\ in the normal-write-transfer cycle, the alternate-write
transfer occurs.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Register-to-memory transfer
(normal write transfer)
Alternate-write transfer
(independent of SE\)
Serial-write-mode enable
(pseudo-transfer write)
Memory-to-register transfer
(normal read transfer)
Split-register-read transfer
(must reload tap)
d(RHSC)
All write-transfer cycles (except the pseudo write transfer)
A normal-write transfer cycle loads the contents of the
During a write-transfer operation before RAS\ falls, the
When DSF is brought high and latched at the falling edge
after RAS goes high (see Figure 6).
FUNCTION
d(SCRL)
but can be resumed after a minimum delay of
Austin Semiconductor, Inc.
CAS\
H
H
H
H
H
TRG\
L
L
L
L
L
RAS\ FALL
W\
H
H
L
L
L
DSF
12
H
H
X
L
L
PSEUDO-WRITE TRANSFER
(write-mode control) (refer to Figure 28)
cycle), SE\ is brought high and latched at the falling edge of
RAS\. The pseudo-write transfer does not actually invoke any
data transfer but switches the mode of the serial port from the
serial-out (read) mode to the serial-in (write) mode.
SDQ terminals and the SC input, the SDQ terminals must be
switched into input mode. Because the transfer does not occur
during the pseudo-transfer write, the row address (A0–A8) is
in the don’t care state and the column address (A0–A8), which
is latched on the falling edge of CAS\, selects one of the 512 tap
points in the SAM that are available for the next serial input.
READ TRANSFER
(DRAM-to-SAM transfer) (refer to Figure 7)
DRAM is transferred to SAM. There are two read-transfer
operations: normal-read transfer and split-register-read
transfer.
NORMAL-READ TRANSFER
(refer to Figure 7)
selected row in DRAM into SAM. TRG\ is brought low and
latched at the falling edge of RAS\. Nine row-address bits
(A0–A8) are also latched at the falling edge of RAS\ to select
one of the 512 rows available for transfer. The nine column-
To invoke the pseudo-write transfer (write-mode control
Before serial data can be clocked into the serial port via the
During a read-transfer cycle, data from the selected row in
The normal-read-transfer operation loads data from a
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SE\
H
L
X
X
X
FALL
CAS\
DSF
X
X
X
X
X
Refresh
RAS\
Addr
Addr
Addr
Addr
Row
Row
Addr
Row
Row
ADDRESS
SMJ44C251B
CAS\
Point
Point
Point
Point
Point
Tap
Tap
Tap
Tap
Tap
MT42C4256
VRAM
VRAM
VRAM
VRAM
VRAM
RAS\
DQ0 - DQ3
X
X
X
X
X
(continued)
CAS\
W\
X
X
X
X
X