MT42C4256C-10/883C AUSTIN [Austin Semiconductor], MT42C4256C-10/883C Datasheet - Page 22

• Manufacturer Part Number: MT42C4256C-10/883C
• Description: 256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM
• Manufacturer: AUSTIN [Austin Semiconductor]

NOTES:
1. Timing measurements are referenced to V
2. All cycle times assume t
3. When the odd tap is used (tap address can be 0–511, and odd taps are 1, 3, 5, etc.), the cycle time for SC in the first serial data out cycle needs to
be 70 ns minimum.
4. In a read-modify-write cycle, t
time [t
5. In a read-modify-write cycle, t
time [t
6. Register-to-memory (write) transfer cycles only
7. The minimum value is measured when t
8. Either t
9. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
10. Read-modify-write operation only
11. TRG\ must disable the output buffers prior to applying data to the DQ terminals.
12. The maximum value is specified only to assure RAS\ access time.
13. CAS\-before-RAS\ refresh operation only
14. Early-load read-transfer cycle only
15. Real-time-reload read-transfer cycle only
16. Late-load read-transfer cycle only
17. In a read-transfer cycle, the state of SC when RAS\ falls is a don’t care condition. However, to assure proper sequencing of the internal clock
circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS\ goes low.
18. In a memory-to-register (read) transfer cycle, t
19. Memory-to-register (read) and register-to-memory (write) transfer cycles only
20. Serial data-in cycles only
21. Switching times assume C
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
w(CL)
w(RL)
h(RHrd)
].
].
or t
(CHrd)
Austin Semiconductor, Inc.
t
must be satisfied for a read cycle.
= 5 ns.
L
= 100 pF unless otherwise noted (see Figure 12).
d(CLWL)
d(RLWL)
and t
and t
d(RLCL)
IL
su(WCH)
su(WRH)
max and V
FIGURE 12: LOAD CIRCUIT
is set to t
d(SCRL)
must be observed. Depending on the user’s transition times, this may require additional CAS\ low
must be observed. Depending on the user’s transition times, this may require additional RAS\ low
applies only when the SAM was previously in serial-input mode.
IH
d(RLCL)
min.
min as a reference.
22
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SMJ44C251B
MT42C4256
VRAM
VRAM
VRAM
VRAM
VRAM