MT42C4256C-10/883C AUSTIN [Austin Semiconductor], MT42C4256C-10/883C Datasheet - Page 43

• Manufacturer Part Number: MT42C4256C-10/883C
• Description: 256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM
• Manufacturer: AUSTIN [Austin Semiconductor]

NOTES:
NOTE N: Late-load operation is defined as t
NOTE O: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written from the 512
corresponding columns of the selected row. The data that is transferred into the data registers may be either shifted out or transferred back into
another row.
NOTE P: Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted out of
the registers. Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
FIGURE 33: Memory-to-Data-Register Transfer-Cycle Timing,
Austin Semiconductor, Inc.
SDQ Ports Previously in Serial-Input Mode
d(THRH)
< 0 ns.
43
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SMJ44C251B
MT42C4256
VRAM
VRAM
VRAM
VRAM
VRAM