MT42C4256C-10/883C AUSTIN [Austin Semiconductor], MT42C4256C-10/883C Datasheet - Page 4

• Manufacturer Part Number: MT42C4256C-10/883C
• Description: 256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM
• Manufacturer: AUSTIN [Austin Semiconductor]

FUNCTION TABLE
NOTES:
1. In persistent write-per-bit function, W\ must be high during the refresh cycle.
2. DQ0 - DQ3 are latched on the later of W\ or CAS\ falling edge. Col Mask = H: Write to address/column location enabled.
3. R = random access operation, T = transfer operation.
LEGEND
H = HIGH
L = LOW
X = Don’t Care
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
CBR Refresh
Register-to-memory transfer
(transfer write)
Alternate transfer write
(independent of SE\)
Serial-write-mode enable
(pseudo-transfer write)
Memory-to-register transfer
(transfer read)
Split-register-transfer read
(must reload tap)
Load and use write mask,
Write data to DRAM
Load and use write mask,
Block write to DRAM
Persistent write-per-bit,
Write data to DRAM
Persistent write-per-bit,
Block write to DRAM
Normal DRAM read/write
(nonmasked)
Block write to DRAM
(nonmasked)
Load write mask
Load color register
DQ Mask = H: Write to I/O enabled.
FUNCTION
Austin Semiconductor, Inc.
CAS\
H
H
H
H
H
H
H
H
H
H
H
H
H
L
TRG\
X
H
H
H
H
H
H
H
L
L
L
L
L
L
RAS\ FALL
W\
X
H
H
H
H
H
H
L
L
L
L
L
L
L
1
DSF
H
H
H
H
H
H
4
X
X
L
L
L
L
L
L
SE\
H
X
X
X
X
X
X
X
X
X
X
X
X
L
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
FALL
CAS\
DSF
X
X
X
X
X
X
H
H
H
H
L
L
L
L
Refresh
Refresh
Refresh
RAS\
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Row
Row
Row
Row
Row
Row
Row
Row
Row
Row
X
ADDRESS
Blk Addr
Blk Addr
Blk Addr
A2-A8
A2-A8
A2-A8
CAS\
Point
Point
Point
Point
Point
Addr
Addr
Addr
Tap
Tap
Tap
Tap
Tap
Col
Col
Col
X
X
X
SMJ44C251B
MT42C4256
RAS\ CAS\
Mask
Mask
DQ0 - DQ3
DQ
DQ
X
X
X
X
X
X
X
X
X
X
X
X
VRAM
VRAM
VRAM
VRAM
VRAM
Mask
Mask
Mask
Mask
Color
Valid
Valid
Valid
Data
Data
Data
Data
Col
Col
Col
DQ
W\
X
X
X
X
X
X
2
TYPE
R
R
R
R
R
R
R
R
R
T
T
T
T
T
3