MC68HC58 Motorola, MC68HC58 Datasheet - Page 74

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MC68HC58

Manufacturer Part Number
MC68HC58
Description
Data Link Controller
Manufacturer
Motorola
Datasheet

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5.2.4 IMOD — Interrupt Mode Bit
5.2.5 OSCD[2:1] — Oscillator Divisor Field
5.2.6 4X — High-Speed Control Bit
5.3 Status Byte
5-8
MOTOROLA
The IMOD bit controls an additional interrupt source to the default interrupt sources.
When IMOD is set, an interrupt request is made when a data byte is received into an
empty RxFIFO buffer. Subsequent bytes do not cause an interrupt request unless the
RxFIFO is emptied before they are received.
The OSCD bit field determines DLC internal clock frequency. The DLC internal clock
frequency is derived from a combination of the external clock frequency and the OSCD
value. Table 5-4 shows frequency division factors and the internal clock frequency
with various references. A 2 MHz internal clock frequency is required for normal oper-
ation.
Setting this bit places the DLC in high-speed data transfer mode. J1850 bus wave-
shaping is disabled.
The status byte register conveys information about data and shows the condition of
the DLC at the time of receipt. Results of commands that are in progress may not be
reflected in the status byte until the command is completely executed.
For a DLC operating in parallel mode, the host MCU can read the status byte alone,
and a subsequent data read automatically flushes the data byte from the buffer.
For a DLC operating in SPI mode, status bytes and received data are transferred to
the host MCU in pairs. When the host reads received data, it remains in the RxFIFO
buffer until a flush command is given. The flush command can accompany the read
command. The DLC does not report the status of an action caused by the current
transfer.
0 = Default interrupts are the only ones enabled
1 = Additional interrupt source added to default sources
0 = Normal clock division
1 = Four times normal clock speed
OSCD
Value
Table 5-4 Internal Clock Frequency Derivations
00
01
10
11
Divisor
Clock
CONTROL AND STATUS CODES
1
2
3
4
0.66 MHz
500 kHz
2 MHz
2 MHz
1 MHz
1.33 MHz
4 MHz
4 MHz
2 MHz
1 MHz
External Clock
1.5 MHz
6 MHz
6 MHz
3 MHz
2 MHz
2.66 MHz
8 MHz
8 MHz
4 MHz
2 MHz
TECHNICAL DATA
MC68HC58

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