MC68HC58 Motorola, MC68HC58 Datasheet - Page 27

• Manufacturer Part Number: MC68HC58
• Description: Data Link Controller
• Manufacturer: Motorola

MC68HC58
TECHNICAL DATA
The following additional guidelines apply to Figure 2-3:
1. Pull-up resistor values depend on electrical characteristics of the host MCU.
2. Exact values for the external components are a function of printed circuit board
3. The example ceramic resonator is a Murata CSA4.00MGA with typical load ca-
4. L1 is a surface mount inductor which should have characteristics similar to TDK
5. An external bias resistor (REXT) determines the waveshape of J1850 bus
6. For maximum noise immunity, V
7. Applications whose requirements for electro-static discharge (ESD) protection
8. One J1850 node in the vehicle typically has a heavier BUS to LOAD pin loading.
9. Although pins 12-19 of the DLC are used only for factory testing, it is recom-
10. Figure 2-3 reflects a configuration for no wake-up upon the detection of J1850
(PCB) capacitance and inductance, socket capacitance, operating voltage and
crystal technology.
pacitance. The DLC contains an internal 1 M
OSC2. No external resistor is required.
NL322522T-470J-3.
signals transmitted by the DLC.
lines; V
tached to the permanent “unswitched” battery supply to take advantage of the
better transient protection found on this circuit rather than the “switched” bat-
tery, or ignition.
exceed the level provided by the bus pin internal circuitry and the bus loading
components may require additional transient protection. The example in Figure
2-3 illustrates this by including two 16-volt zener diodes placed between the bus
and ground. These diodes (part # P4SMA16AT3) should be located as close to
the module connector as possible. Refer to APPENDIX A ELECTRICAL
CHARACTERISTICS for information on maximum voltage ratings.
This allows a smaller differential between the total network load of two nodes
versus 32 nodes. If 26 nodes or more are used, the heavier loading should not
be present as this may violate the maximum capacitance and minimum resis-
tance allowed by the J1850. A network of 26 or more nodes should all have the
lower load values.
mended that these pins be tied to ground in the application. This prevents ad-
ditional current from being consumed by the DLC, particularly when the low-
power standby mode is utilized.
bus activity. If system wake-up upon the detection of J1850 bus activity is de-
sired, perform the following:
• Tie the V
• Tie the PSEN pin on the DLC through a 33 k resistor to the ignition input of
• Tie the V
down when the DLC is placed in the standby mode.
the power supply/regulator. This limits the current sourced by the DLC. This
resistor value should be determined by the individual application. A 10 k
pull-down resistor should be included from the PSEN line to ground. A 100 k
resistor from the RST pin to ground should also be added.
the DLC to a separate 5 Vdc power supply. This 5 Vdc power supply remains
powered up when the rest of the node is powered down.
SSA
DD
CC
and V
pin to a 5 Vdc power supply. This 5 Vdc power supply is powered
pin and the pull-up points for the external bias resistor (REXT) on
SSD
SIGNAL AND PIN DESCRIPTIONS
should also be separate. The V
CC
and V
DD
should be supplied by separate
resistor across OSC1 and
BATT
pin is shown at-
MOTOROLA
2-11