MC68HC58 Motorola, MC68HC58 Datasheet - Page 60

• Manufacturer Part Number: MC68HC58
• Description: Data Link Controller
• Manufacturer: Motorola

4.4 Receiver Operation
4-16
MOTOROLA
The DLC receiver continuously monitors the J1850 bus for voltage swings of 0.375
volts centered around 3.875 Vdc. It converts these swings to full logic level transitions,
which are then clocked through a digital filter into the receiver. Duration of the filtered
J1850 bus states are timed by the control logic and compared to a set of received
symbol threshold windows. Each J1850 bus state is translated into one of the symbols
or is flagged as a timing error. The receiver considers the J1850 bus to be idle when
it has been in the passive state for a predetermined time.
Once an SOF symbol is detected, the receiver stores frame bytes as they are received
in the RxFIFO buffer until an EOD symbol is detected, or until the RxFIFO buffer is full.
As each byte is received, the DLC status is updated to reflect the state of the RxFIFO
(the status is updated each clock cycle during the frame).
When all frame bytes have been received, the receiver checks the CRC, but does not
place it in the RxFIFO buffer. Instead, it appends a completion code byte to the frame.
The byte contains information about the frame.
The DLC receiver performs two basic error detection functions during message
transmission and reception. These two error detection mechanisms are:
The digital filter eliminates J1850 bus noise spikes and transition noise lasting less
than the propagation delay through the J1850 transceiver. Filter operation is best de-
scribed as a logic-level detector and a 4-bit counter. The counter counts up when the
J1850 bus is active (logic level one is detected), and counts down when the J1850 bus
is passive (logic level zero is detected). If a full count (0 or 15) occurs, the J1850 bus
state transition is considered to be valid, and the signal transition passes to the receiv-
er. As a result, the filter introduces a receive time-delay of 15 to 16 times the internal
clock period. With a 2 MHz clock, the clock period is 0.5 s, so the filter time delay is
approximately 8 s.
Each DLC receives every frame on the J1850 bus, including those it transmits. At the
end of each reception from the J1850 bus, the receiver places a completion code byte
into the RxFIFO immediately following that frame. This byte contains transmitter action
codes, in-frame response codes, and error codes. When a DLC is transmitting, the
completion code information applies to both the transmitter and receiver. Completion
code bytes are also placed in the RxFIFO when errors are detected, but the host MCU
must read and interpret the codes to determine the nature of the error. Available error
information includes receiver overrun, transmitter underrun, loss of arbitration, incor-
rect CRC, incomplete byte indication, and bit timing error. Refer to SECTION 5 CON-
TROL AND STATUS CODES for more information.
A host MCU can monitor the receiver by polling status bytes, or servicing can be inter-
rupt driven. When interrupts are enabled, an interrupt request can be generated by the
receiver in the following circumstances:
• The digital input filter
• The receiver J1850 bus monitor
DATA LINK CONTROLLER OPERATION
TECHNICAL DATA
MC68HC58