MC68HC58 Motorola, MC68HC58 Datasheet - Page 56

• Manufacturer Part Number: MC68HC58
• Description: Data Link Controller
• Manufacturer: Motorola

4.3 Transmitter Operation
4-12
MOTOROLA
When a condition that would normally cause an interrupt request occurs while the chip
select input is asserted, the DLC cannot assert INT until the logic level on the CS pin
returns to one.
In default configuration, the DLC asserts INT under the following circumstances (a 4
MHz reference is assumed):
The host MCU must use information in the status byte or the completion code to de-
termine the interrupt source. It cannot deduce the cause of a TxFIFO half empty inter-
rupt during block mode transmission because there is no explicit status indication for
a TxFIFO buffer underrun. The host MCU can, however, monitor DLC status bytes for
an indication that the TxFIFO buffer is no longer full.
The DLC transmitter drives the J1850 bus to at least 6.25 Vdc, and expects the exter-
nal load to pull the J1850 bus down below 1.5 Vdc. The transmitter responds to feed-
back from the receiver in order to determine precisely when to start and finish driving
the bus. A set of basic transmit timing windows for J1850 bus symbols is stored in the
DLC logic. The transmitter uses these timing windows as a basis for transmission, but
if the receiver detects a change in the J1850 bus state during transmission, the trans-
mitter switches to that state unless the switch causes the transmitter to lose arbitration.
If arbitration is lost, the transmitter halts. This mechanism prevents J1850 bus conflict
due to slight timing differences between J1850 bus nodes. Only one frame appears on
the J1850 bus during a transmission. Symbols in the frame are driven and released by
all participating nodes, but the end result is a single waveform.
To transmit a frame on the J1850 bus, a host MCU first transfers frame data to the
DLC. For parallel mode, a command byte need only accompany and identify the first
and last byte(s). For serial mode, each byte of data must be accompanied by a
command byte that tells the DLC whether the data is a first, intermediate, or last byte.
• When a frame completion code is placed in the RxFIFO. The DLC asserts INT
• When the RxFIFO buffer has 12 bytes in it and a 13th byte is received. The DLC
• When the TxFIFO is half emptied during a block mode transmission (no byte in
• When the DLC comes out of standby mode due to activity on the SAE J1850 bus.
• After a configuration byte with IMOD set is sent to a DLC, the DLC also asserts
within 10 s of sensing EOD on the J1850 bus.
asserts INT within 15 s after the trailing edge of the first bit of the 14th byte re-
ceived.
the TxFIFO buffer has been accompanied by a “load a last byte of transmit data”
command). Six bytes remain to be transmitted when the interrupt request is
made. The DLC asserts INT within ten s after the trailing edge of the last bit of
the fifth byte transmitted.
The DLC asserts INT within 105 s after the passive to active level of the SOF
symbol.
INT when a byte is received into an empty RxFIFO. INT assertion occurs 15 s
or less after the trailing edge of the first bit of the second byte received.
DATA LINK CONTROLLER OPERATION
TECHNICAL DATA
MC68HC58