MC68HC58 Motorola, MC68HC58 Datasheet - Page 49

• Manufacturer Part Number: MC68HC58
• Description: Data Link Controller
• Manufacturer: Motorola

4.2.1 MC68HC58 DLC Parallel Mode Host MCU Interface
4.2.1.1 Parallel Mode Data Transfer
MC68HC58
TECHNICAL DATA
The host MCU can put a DLC in standby mode by sending it the “enter standby mode”
command byte. The DLC completes all current frames, then goes inactive. PSEN
sources V
standby mode. An incoming bus frame, or the host MCU asserting CS and reading the
status byte, can reactivate a DLC.
The DLC interface is designed to work with an M6800 bus clock signal (CLK), but
functions equally well with any host MCU that meets timing requirements. Refer to AP-
PENDIX A ELECTRICAL CHARACTERISTICS for more parallel host interface timing
information.
Parallel mode transfers are controlled by the R/W and ADDR0 signals from the host
MCU. R/W and ADDR0 determine which of four possible bytes are being transferred.
Figure 4-4 shows the parallel mode byte format.
INTERFACE
INTERRUPT
LINE INT
HOST
BUS
CS
BYTES TRANSMITTED,
RECEIVED, AND PLACED
INTO RXFIFO
HOST INTERFACE ACTIVITY TO
TRANSFER MESSAGE INTO DLC
FOR TRANSMISSION
BATT
while the DLC is active and goes to a high-impedance state during
DATA LINK CONTROLLER OPERATION
Figure 4-3 DLC Operation
MESSAGE ON BUS
HOST INTERFACE
ACTIVITY
BUS ACTIVITY
LAST BYTE OF MESSAGE AND
COMPLETION CODE PLACED
IN RXFIFO INTERRUPT ASSERTED
HOST INTERFACE ACTIVITY TO
TRANSFER RECEIVED MESSAGE
OUT OF DLC
INTERRUPT
CLEARED BY CS
AND STATUS READ
DLC OPERATION
MOTOROLA
4-5