ADMC300-PB Analog Devices, ADMC300-PB Datasheet - Page 8

• Manufacturer Part Number: ADMC300-PB
• Description: High Performance DSP-Based Motor Controller
• Manufacturer: Analog Devices

ADMC300
DSP CORE ARCHITECTURE OVERVIEW
Figure 3 is an overall block diagram of the DSP core of the
ADMC300, which is based on the fixed-point ADSP-2171. The
ADSP-2171 flexible architecture and comprehensive instruction
set allows the processor to perform multiple operations in paral-
lel. In one processor cycle (40 ns with a 12.5 MHz CLKIN) the
DSP core can:
• Generate the next program address.
• Fetch the next instruction.
• Perform one or two data moves.
• Update one or two data address pointers.
• Perform a computational operation.
This all takes place while the processor continues to:
• Receive and transmit through the serial ports.
• Decrement the interval timer.
• Generate PWM signals.
• Convert the ADC input signals.
• Operate the encoder interface unit.
• Operate all other peripherals including the auxiliary PWM and
event timer subsystem.
GENERATOR
OUTPUT REGS
ADDRESS
INPUT REGS
DATA
#1
ALU
GENERATOR
ADDRESS
DATA
#2
OUTPUT REGS
INPUT REGS
MAC
16
R BUS
SEQUENCER
INSTRUCTION
PROGRAM
REGISTER
OUTPUT REGS
INPUT REGS
EXCHANGE
SHIFTER
BUS
14
14
24
16
PM ROM
PM RAM
2K
4K
CONTROL
LOGIC
The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported.
The MAC performs single-cycle multiply, multiply/add, multiply/
subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denormal-
ization, and derive exponent operations. The shifter can be used
to efficiently implement numeric format control including floating-
point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa-
tional units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMC300 executes looped code
with zero overhead; no explicit jump instructions are required
to maintain the loop.
24
24
DMA BUS
PMD BUS
PMA BUS
DMD BUS
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
5
COMPANDING
DM RAM
1K
CIRCUITRY
16
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
6
TIMER