ADMC300-PB Analog Devices, ADMC300-PB Datasheet - Page 3

• Manufacturer Part Number: ADMC300-PB
• Description: High Performance DSP-Based Motor Controller
• Manufacturer: Analog Devices

ANALOG-TO-DIGITAL CONVERTER
Parameter
Signal-to-Noise Ratio
Total Harmonic Distortion
Common-Mode Rejection Ratio
Channel-Channel Crosstalk
Gain Error
Gain
V
V
V
f
f
V
R
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
VOLTAGE REFERENCE
Parameter
V
Power Supply Rejection Ratio (PSRR)
Specifications subject to change without notice.
PULSEWIDTH MODULATOR
Parameter
T
T
f
T
f
NOTES
1
Specifications subject to change without notice.
MOD, MAX
S, MAX
SNR measured with ADC channel configured in single-ended mode. SNR measurement does not include harmonic distortion, THD includes first six harmonics.
Input signal applied to both pins of input differential pair of ADC channel.
Input signal applied to four ADC channels, dc applied to fifth, measurement taken at fifth ADC channel.
Peak-peak input voltage in differential input configuration is half that in single-ended mode.
This offset may be corrected for, using the ADC calibration feature.
At maximum sigma-delta modulator rate of 2.08 MHz.
Input reference pins: REFINA, REFINB.
Analog signal input pins: V1–V5, V1N–V5N.
PWM
CHOP
Resolution varies with PWM switching frequency, 191 Hz = 16 bits, 3.05 kHz = 12 bits, 48.8 kHz = 8 bits (12.5 MHz CLKIN) in single update mode.
The effective number of bits (ENOB) is related to the SNR by SNR = 6.02 (ENOB) +1.76 dB. Input signal filtered at 1.5 kHz.
IN
DIFF
OFFSET
REFIN
IN
REF
D
MIN
SYNC
Analog Input Range
Analog Input Voltage (Differential)
DC Offset Voltage
Maximum Sigma-Delta Modulator Rate
Maximum ADC Sample Rate
Reference Input Voltage
Equivalent Input Resistance
Voltage Level
Source Current
Counter Resolution
Edge Resolution
Programmable Dead Time
Programmable Dead Time Increments
Programmable Pulse Deletion
Programmable Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth
Gate Drive Chop Frequency
1
(SNR)
1
3
(THD)
2
(V
noted)
(CMRR)
5
1
4
DD
= AV
1
7
(V
otherwise noted)
DD
DD
8
= 5 V
= AV
6
DD
(V
CLKIN = 12.5 MHz, unless otherwise noted)
4
= 5 V
DD
10%, GND = AGND = 0 V, T
= AV
DD
10%, GND = AGND = 0 V, T
Test Conditions
@V
@ f
@ f
ADCDIVn = 0x180,
V1–V5 = 4.0 V p-p
V1N–V5N = V
ADCDIVA = 0x180
ADCDIVB = 0x180
ADCDIVA = 0x180
ADCDIVB = 0x180
= 5 V
Test Conditions
Test Conditions
Double Update Mode
S
IN
DD
= 32.55 kHz,
= 1.017 kHz,
= 5.0 V,
10%, GND = AGND = 0 V, V
REFIN
AMB
= –40 C to +85 C, CLKIN = 12.5 MHz, unless otherwise
= 2.5 V
AMB
= –40 C to +85 C, CLKIN = 12.5 MHz, unless
REFIN
Min
72
0
2.4
Min
2.25
–5
Min
0
0
191
0.04
0.0244
= 2.50 V, T
Typ
76
2.5
25
Typ
Typ
10,600
40
80
40
AMB
= –40 C to +85 C,
Max
–70
–82
–76
5
V
V
55
2.08
32.55
2.6
Max
2.75
–100
5
Max
16
81.84
40.92
10.24
6.25
DD
DD
ADMC300
/2
Unit
dB
dB
dB
dB
%
LSB/V
V
V
mV
MHz
kHz
V
kΩ
Unit
V
µA
mV/V
Unit
Bits
ns
µs
ns
µs
ns
Hz
µs
MHz