ADMC300-PB Analog Devices, ADMC300-PB Datasheet - Page 24

• Manufacturer Part Number: ADMC300-PB
• Description: High Performance DSP-Based Motor Controller
• Manufacturer: Analog Devices

ADMC300
Encoder Counter Reset
The ZERO bit (Bit 1) of the EIUCTRL register determines if
the encoder zero marker is used to reset the up/down counter of
the encoder interface. When Bit 1 of the EIUCTRL register is
set, the zero marker signal is used to reset the up/down counter
to zero (if moving in the forward direction) or to the value in
the EIUMAXCNT register (if moving in the reverse direction).
The reset operation takes place on the next quadrature pulse
after the zero marker has been recognized. In order to ensure
correct encoder counting (no missing or spurious codes) the
logic in the encoder counter latches the conditions (appropriate
encoder edge) at which the first reset is performed. Thereafter,
irrespective of operating conditions, the encoder reset operation
is always aligned with the same encoder edge. For example, if
the first reset operation occurs on the rising edge of B and the
encoder is moving in the forward direction, then all subsequent
reset operations are aligned with the rising edge of the B signal
(while moving in the forward direction) and on the falling edge
of B for rotation in the reverse direction. In order to account for
zero marker signals of different widths, the zero marker will be
recognized as the rising edge of the EIZP signal when moving in
the forward direction. When moving in the reverse direction, the
zero marker is recognized at the falling edge of the signal at the
EIZP pin.
When the ZERO bit of the EIUCTRL register is cleared, the
zero marker is not used at all by the encoder interface circuitry.
In this mode, the contents of the EIUMAXCNT register are
used as the reset value for the up/down counter. For example,
for an N-line incremental encoder, the appropriate value to
write to the EIUMAXCNT register is 4N-1. Therefore, for a
1024 line encoder, a value of 0x0FFF (= 4095) would be writ-
ten to the EIUMAXCNT register. However, since absolute
position information is not available in this mode, due to the
absence of the zero marker, the full 16-bit range of the quadra-
ture counter may be employed by writing a value of 0xFFFF to
the EIUMAXCNT register. Following a reset, the ZERO bit is
cleared.
The value written to the EIUMAXCNT register must be in the
form 4N-1, where N is any integer.
Single North Marker Mode
A further reset mode is available in the Encoder Interface Unit
called Single North Marker Mode. This mode is enabled by set-
ting Bit 2 (SNM) of the EIUCTRL register. For this mode to
operate, the ZERO bit (Bit 1) of the EIUCTRL register must
also be set. In this mode the EIUCNT register is reset (to zero
or EIUMAXCNT depending on direction) only on the first
occurrence of the zero marker. Subsequently, the EIUCNT regis-
ter is reset by the natural roll-over to zero or the value in the
EIUMAXCNT register. Following a reset, this SNM bit is
cleared.
Bit 6 of the EIUSTAT register is used to signal the first occur-
rence of a zero marker. When the first zero marker has been
recognized by the EIU, Bit 6 of the EIUSTAT register is set.
Encoder Error Checking
Error checking in the EIU is enabled by setting Bit 3 (MON) of
the EIUCTRL register. The ZERO bit of the EIUCTRL regis-
ter must also be set for error checking to be enabled. In this mode,
the contents of the EIUCNT register are compared with the
expected value (zero or EIUMAXCNT depending on direction)
when the zero marker is detected. If a value other than the ex-
pected value is detected, an error condition is generated by
setting Bit 0 of the EIUSTAT register and triggering an EIU
interrupt. Since the EIU interrupt can be initiated by both this
error checking function and the time-out of the encoder loop
timer, this status bit must be read to determine the source of the
interrupt if both are possible. Obviously if the encoder loop
timer is disabled, the EIU interrupt can only be generated by
this error-checking function. This EIU interrupt is also managed
and may be masked by the programmable interrupt controller
(PIC) block. The encoder continues to count encoder edges
after an error has been detected. Bit 0 of the EIUSTAT register
is cleared on the occurrence of the next zero marker provided
the error condition no longer exists and the EIUCNT register
again matches the expected value. Following a reset, the MON
bit is cleared.
Encoder Pin Status
Three additional status bits are provided in the EIUSTAT regis-
ter that provide a measure of the state of the three EIU pins
(EIA, EIB and EIZP) following the synchronization buffers.
Bit 3 indicates the state of the EIA pin, Bit 4 indicates the state
of the EIB pin and Bit 5 gives the state of the EIZP pin. The
value of these status bits read is not affected by any of the con-
trol bits in the EIUCTRL register.
EIA
EIB
EIZP
ENCODER
LOOP
TIMER
ENCODER
INTERFACE
BLOCK
CLKIN
EIUPERIOD (15…0)
EIUTIMER (15…0)
EIUSCALE (7…0)
SYNCHRONIZA-
EIUSTAT(5…3)
BUFFERS
TION
TIMEOUT
ZP
A
B
MON
DIRECTION
QUADRATURE
EIUCTRL(5…0)
ENCODER EVENT
SNM
CLOCK DIVIDER
CHECKING
CLK
COUNTER
ENCODER
COUNTER
UP/DOWN
ERROR
16-BIT
ZERO
TIMER
DECIMATOR
REV
PULSE
QUADRATURE SIGNAL
ENCODER EVENT TIMER BLOCK
EETDELTAT(15…0)
EIUMAXCNT(15…0)
OR
EETCNT(15…0)
EIUSTAT(2…0)
EETDIV(15…0)
EIUCNT(15…0)
EETSTAT(0)
EETT(15…0)
EETN(7…0)
INTERRUPT
MEMORY BUS
DSP DATA
EIU