ADMC300-PB Analog Devices, ADMC300-PB Datasheet - Page 40

• Manufacturer Part Number: ADMC300-PB
• Description: High Performance DSP-Based Motor Controller
• Manufacturer: Analog Devices

ADMC300
Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a
gray field – these bits should always be written as shown.
SPORT1 RECEIVE OR IRQ0
SOFTWARE 1
SPORT1 TRANSMIT OR IRQ1
TIMER
INTERRUPT FORCE
SPORT0 TRANSMIT
SPORT0 RECEIVE
SOFTWARE 0
IRQ2
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
(MASK)
(MASK)
0 = DISABLE
1 = ENABLE
15
0
15
15
0
0
SOFTWARE 1
PERIPHERAL (OR IRQ2)
SPORT0 RECEIVE
RESERVED (SET TO 0)
SPORT0 TRANSMIT
14
0
14
14
0
0
PIO2
PIO3
PIO0
EVENT TIMER
PIO1
PWMTRIP
13
13
0
13
0
0
INTERRUPT NESTING
12
12
0
12
0
0
11
11
0
0
11
0
10
10
0
0
10
0
9
0
9
0
9
0
PICMASK (R/W)
IMASK (R/W)
0
8
0
4
0
8
0
8
IFC
7
0
3
0
7
0
7
0
ICNTL
0
2
6
0
6
0
6
0
1
1
5
0
5
0
5
0
1
0
4
0
4
0
4
0
DSP REGISTER
IRQ1 SENSITIVITY
IRQ2 SENSITIVITY
IRQ0 SENSITIVITY
0
3
0
3
3
0
2
0
2
1
2
0
1
0
1
1
1
0
0
0
0
0
0
0
DSP REGISTER
TIMER
SPORT1 RECEIVE OR IRQ0
SOFTWARE 1
SPORT0 RECEIVE
SPORT0 TRANSMIT
IRQ2
SPORT1 TRANSMIT OR IRQ1
SOFTWARE 0
TIMER
SPORT1 RECEIVE
(OR IRQ0)
SPORT1 TRANSMIT
(OR IRQ1)
SOFTWARE 0
ADC BANK A
PWMSYNC
ADC BANK B
PIO (PIO4 TO PIO11)
ENCODER INTERFACE
DSP REGISTER
0 = LEVEL
1 = EDGE
DM (0x201D)
INTERRUPT CLEAR
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
(MASK)
(MASK)