ADMC300-PB Analog Devices, ADMC300-PB Datasheet - Page 12

• Manufacturer Part Number: ADMC300-PB
• Description: High Performance DSP-Based Motor Controller
• Manufacturer: Analog Devices

ADMC300
program and data memory RAM can be loaded from the SROM/
E
begins at address 0x0060. This is where the first instruction of
the user code should be placed.
If boot loading from an E
code reconfigures SPORT1 as a UART and attempts to receive
commands from an external device on this serial port. The
monitor then waits for a byte to be received over SPORT1,
locks onto the baud rate of the external device (autobaud fea-
ture) and takes in a header word that tells it with what type of
device it is communicating. There are six alternatives:
• A UART boot loader such as a Motorola 68HC11 SCI port.
• A synchronous slave boot loader (the clock is external).
• A synchronous master boot loader (the ADMC300 provides
• A UART debugger interface.
• A synchronous master debugger interface.
• A synchronous slave debugger interface.
With the debugger interface, the monitor enters interactive
mode in which it processes commands received from the
external device.
2
the clock).
PROM. After the boot load is complete, program execution
REFINA
REFINB
CONVST(PIO9)
V1N
V2N
V3N
V4N
V5N
V1
V2
V3
V4
V5
MUX0
MUX1
MUX2
ADCCAL (4…0)
MULTIPLEXER
CALIBRATION
2
PROM is unsuccessful, the monitor
MULTIPLEXER
CONTROL
16-BIT
16-BIT
16-BIT
16-BIT
16-BIT
UPDATE CONTROL
ADC BANKA
ADC BANKB
ADCCTRL (15…0)
ADC REGISTER
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT0 is enabled when Bit 12 is
set, disabled when this bit is cleared. SPORT1 is enabled when
Bit 11 is set, disabled when this bit is cleared. SPORT1 is con-
figured as a serial port when Bit 10 is set, or as flags and inter-
rupt lines when this bit is cleared. For proper operation of the
ADMC300, all other bits in this register must be cleared (which
is their default).
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). For proper operation of the
ADMC300, this register must always contain the value 0x8000
(which is the default).
The configuration of both the SYSCNTL and MEMWAIT
registers of the ADMC300 is shown at the end of the data sheet.
ANALOG-TO-DIGITAL CONVERSION SYSTEM
A functional block diagram of the ADC system of the ADMC300
is shown in Figure 5. The ADC system provides the high perfor-
mance conversion required for precision applications. It integrates
five completely independent analog-to-digital converters based
on sigma-delta conversion technology. Each ADC channel may
UPDATE
ADC2 (15…0)
ADC1 (15…0)
ADC3 (15…0)
ADC4 (15…0)
ADC5 (15…0)
ADCDIVA (11…6)
ADCDIVB (11…6)
ADCSYNC (6…0)
GENERATOR
REFERENCE
INTERNAL
VOLTAGE
DSP DATA
MEMORY
BUS
V
REF