ADMC300-PB Analog Devices, ADMC300-PB Datasheet - Page 20

• Manufacturer Part Number: ADMC300-PB
• Description: High Performance DSP-Based Motor Controller
• Manufacturer: Analog Devices

ADMC300
The minimum permissible T
sponding to a 0% duty cycle. In a similar fashion, the maximum
value is T
The output signals from the timing unit for operation in double
update mode are shown in Figure 13. This illustrates a com-
pletely general case where the switching frequency, dead time
and duty cycle are all changed in the second half of the PWM
period. Of course, the same value for any or all of these quanti-
ties could be used in both halves of the PWM cycle. However, it
can be seen that there is no guarantee that symmetrical PWM
signals will be produced by the timing unit in double update
mode. Additionally, it is seen that the dead time is inserted into
the PWM signals in the same way as in the single update mode.
In general the on-times of the PWM signals in double update
mode can be defined as:
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
since for the completely general case in double update mode, the
switching period is given by:
Again, the values of T
zero and T
PWM signals similar to those illustrated in Figure 12 and Figure
13 can be produced on the BH, BL, CH and CL outputs by
programming the PWMCHB and PWMCHC registers in a
manner identical to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB and PWMCHC
registers have been written to at least once. Once these registers
d
d
SYSSTAT (3)
AL
AH
PWMSYNC
T
=
T
=
AH
T
T
AL
–PWMDT
T
S
T
AL
T
d
= (PWMCHA
S
AH
=
AH
AL
S
AL
(
= (PWMTM
S
= (PWMTM
PWMTM
, corresponding to a 100% duty cycle.
S
=
.
2
=
(
T
PWMCHA
T
PWMDT
1
AL
PWMSYNCWT
S
– PWMDT
1
+
PWMTM
=
PWMTM
1
PWMTM – PWMCHA – PWMDT
1
1
+ PWMCHA
AH
+ PWMTM
1
+ PWMTM
1
1
PWMCHA
and T
+
2
(
1
2
PWMTM
–
PWMCHA
+ 1
) ×
(
PWMCHA
AH
PWMTM
t
CK
AL
and T
1
2
2
PWMTM
– PWMCHA
are constrained to lie between
– PWMDT
PWMCHA
1
1
1
2
+
–
)× t
+
AL
PWMTM
2
PWMCHA
PWMTM
–
values are zero, corre-
CK
PWMDT
2
PWMTM
PWMSYNCWT
1
2
)
– PWMDT
1
2
– PWMCHA
–
PWMDT
2
2
1
)
2
–
PWMDT
PWMDT
2
1
+ 1
–
2
) × t
PWMDT
2
2
CK
2
)
2
)
have been written, internal counting of the timers in the
three-phase timing unit is enabled. Writing to the PWMTM
register starts the internal timing of the main PWM timer. Pro-
vided the PWMTM register is written prior to the PWMCHA,
PWMCHB and PWMCHC registers in the initialization,
the first PWMSYNC pulse and interrupt (if enabled) appear
1.5 × t
PWMTM register in single update mode. In double update
mode, the first PWMSYNC pulse appears after PWMTM ×
t
Effective PWM Resolution
In single update mode, the same value of PWMCHA, PWMCHB
and PWMCHC is used to define the on-times in both half
cycles of the PWM period. As a result the effective resolution
of the PWM generation process is 2t
CLKOUT), since incrementing one of the duty cycle registers
by one changes the resultant on-time of the associated PWM
signals by t
In double update mode, improved resolution is possible since
different values of the duty cycle registers are used to define the
on-times in both the first and second halves of the PWM pe-
riod. As a result, it is possible to adjust the on-time over the
whole period in increments of t
effective PWM resolution of t
40 ns for a 25 MHz CLKOUT).
The achievable PWM switching frequency at a given PWM
resolution is tabulated in Table V.
Table V. Achievable PWM Resolution in Single and Double
Update Modes
Resolution
(Bits)
8
9
10
11
12
Minimum Pulsewidth, PWMPD Register
In many power converter switching applications, it is desirable
to eliminate PWM switching signals below a certain width. It
takes a certain finite time to both turn on and turn off modern
power semiconductor devices. Therefore, if the width of any of
the PWM signals goes below some minimum value, it may be
desirable to completely eliminate the PWM switching for that
particular cycle.
The allowable minimum on-time for any of the six PWM out-
puts over half a PWM period that can be produced by the
PWM controller may be programmed using the PWMPD regis-
ter. The minimum on-time is programmed in increments of t
so that the minimum on-time that will be produced over any
half PWM period, T
register by:
so that a PWMPD value of 0x002 defines a permissible mini-
mum on-time of 80 ns for a 25 MHz CLKOUT.
CK
seconds.
CK
× PWMTM seconds after the initial write to the
CK
in each half period (or 2t
Single Update Mode
(kHz)
48.8
24.4
12.2
6.1
3.05
PWM Frequency
MIN
T
MIN
, is related to the value in the PWMPD
= PWMPD × t
CK
CK
in double update mode (or
. This corresponds to an
CK
CK
(or 80 ns for a 25 MHz
Double Update Mode
(kHz)
97.6
48.8
24.4
12.2
6.1
PWM Frequency
CK
for the full period).
CK