ADMC300-PB Analog Devices, ADMC300-PB Datasheet - Page 27

• Manufacturer Part Number: ADMC300-PB
• Description: High Performance DSP-Based Motor Controller
• Manufacturer: Analog Devices

internal pull-down resistors, any unconnected PIO lines will
cause a PWM trip. Therefore, prior to using the PWM unit of
the ADMC300, it is imperative that the PIO state be correctly
configured for the particular application.
PIO Registers
The configuration of all registers associated with the PIO sys-
tem are shown at the end of the data sheet. Each of the registers
has a bit directly associated with one of the PIO lines. For ex-
ample, Bit 0 of all registers affects only the PIO0 line of the
ADMC300.
AUXILIARY PWM OUTPUTS
The ADMC300 provides two auxiliary, fixed-frequency, vari-
able duty cycle PWM outputs that may be used to drive auxil-
iary switching circuits in the motor control system. Alternatively,
by adding appropriate filtering at the output, these signals can
be used to provide a simple digital-to-analog converter. These
output signals appear on the AUX0 and AUX1 pins and are con-
trolled by the duty cycle registers, AUXTIM0 and AUXTIM1.
The auxiliary PWM outputs operate at a fixed frequency that is
f
48.8 kHz for a 12.5 MHz CLKIN. The output duty cycle at the
auxiliary PWM output pin is controlled by comparing the 8-bit
auxiliary PWM duty-cycle registers, AUXTIM0 and AUXTIM1
with the contents of a timer. The value written to these registers
may range from 0 to 255 so that duty cycles from 0 to 99.6%
may be produced at the output pins. A simple filter at the
output could then be used to produce a corresponding analog
output from 0 to 0.996 V
The outputs of the two auxiliary PWM timer circuits are synchro-
nized on their rising edges. When the auxiliary timer registers are
written to, the value becomes effective immediately. Therefore,
if the value is smaller than the present timer value, the outputs
go low immediately. The correct duty cycle appears for the
subsequent auxiliary PWM period. On reset, the AUXTIM0
and AUXTIM1 registers are cleared so that no auxiliary PWM
signals are produced and the AUX0 and AUX1 pins are low
until these registers are programmed. The format of the
AUXTIM0 and AUXTIM1 registers is shown at the end of the
data sheet.
WATCHDOG TIMER
The ADMC300 incorporates a watchdog timer that can per-
form a full reset of the DSP and motor control peripherals in
the event of software error. The watchdog timer is enabled by
writing a timeout value to the 16-bit WDTIMER register. The
timeout value represents the number of CLKIN cycles required
for the watchdog timer to count down to zero. When the
watchdog timer reaches zero, a full DSP core and motor control
peripheral reset is performed. In addition, Bit 1 of the SYSSTAT
register is set so that after reset the ADMC300 can determine
that the reset was due to the time out of the watchdog timer and
not a power-on reset. Following a reset, Bit 1 of the SYSSTAT
register may be cleared by writing zero to the WDTIMER regis-
ter. This clears the status bit but does not enable the watchdog
timer.
On reset, the watchdog timer is disabled and is only enabled
when the first timeout value is written to the WDTIMER
register. To prevent the watchdog timer from timing out, the
user must write to the WDTIMER register at regular intervals
CLKIN
/256. This gives an auxiliary PWM switching frequency of
DD
.
(shorter than the programmed WDTIMER period value). On all
but the first write to WDTIMER, the particular value written to
the register is unimportant since writing to WDTIMER simply
reloads the first value written to this register.
EVENT TIMER UNIT
The ADMC300 contains a dual channel Event Timer Unit
(ETU) that may be used to accurately measure the elapsed time
between defined events on a particular channel. The ETU uses
two input pins, ETU0 and ETU1, that are multiplexed with the
PIO10 and PIO11 pins. The ETU system contains a set of
16-bit data registers that are used to store the value of the
dedicated ETU timer on the occurrence of the defined events
on the input pins. A configuration register is used to define the
nature of the events on each of the input pins. In addition, a
control register is used to initiate event capture on the inputs. A
status register may be read to determine the state of the two
capture channels. A dedicated ETU interrupt may be generated
upon completion of a capture sequence on either the ETU0 or
ETU1 channel.
The ETU timer is a free running counter whose contents may be
read from the 16-bit ETUTIME read only register.
An event may be defined as either a rising or falling edge on the
associated ETU0 and ETU1 inputs pins. Therefore, the ETU
system can be used to compute the frequency, period, duty
cycle or on-time of signals applied at the inputs. A functional
block diagram of the ETU system of the ADMC300 is shown
in Figure 18.
ETU Event Definition
The ETU system of the ADMC300 contains a dedicated 16-bit
timer whose clock frequency may be programmed using the
ETUDIVIDE register. This register divides the CLKIN frequency
to provide the clock signal for the ETU timer. The clock
frequency of the ETU timer may be expressed as f
ETUDIVIDE and is common to both channels.
Two events are used to trigger the ETU, termed Event A and
Event B. By setting the appropriate bits of the ETUCONFIG
register, it is possible to define both Events A and B as either
rising or falling edges on the appropriate pin. For example,
setting Bit 0 of the ETUCONFIG register defines Event A of
the ETU0 channel as a rising edge on the ETU0 pin. Similarly,
setting Bit 4 of the ETUCONFIG register defines Event A of
the ETU1 channel as a rising edge on the ETU1 pin. Event A
defines the start of the event capture sequence. Associated with
each ETU channel are three data registers, ETUA0, ETUB0
and ETUAA0 for ETU Channel 0 and ETUA1, ETUB1 and
ETUAA1 for ETU Channel 1. These data registers store the
ETU timer value on the occurrence of the first A Event, the first
B Event and the second A Event respectively. For example, for
ETU Channel 0, ETUA0 stores the timer value on the first
occurrence of Event A on the ETU0 pin, ETUB0 stores the
timer value on the first occurrence of Event B on the ETU0 pin
and ETUAA0 stores the timer value on the second occurrence
of Event A on the ETU0 pin. Registers ETUA1, ETUB1 and
ETUAA1 perform the same function for events on ETU
Channel 1.
Because the ETU0 and ETU1 pins are multiplexed with the
PIO10 and PIO11 pins, it is possible to configure these lines as
ADMC300
CLKIN
/