ADMC300-PB Analog Devices, ADMC300-PB Datasheet - Page 41

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ADMC300-PB

Manufacturer Part Number
ADMC300-PB
Description
High Performance DSP-Based Motor Controller
Manufacturer
Analog Devices
Datasheet
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field – these
bits should always be written as shown.
0 = DISABLED
1 = ENABLED
0 = DISABLED
1 = ENABLED
SPORT0 ENABLE
SPORT1 ENABLE
15
15
15
15
0
1
1 = DOUBLE UPDATE
0 = SINGLE UPDATE
14
14
14
14
0
1 = SECOND HALF CYCLE
0 = FIRST HALF CYCLE
0
13
13
13
13
0
0
12
12
12
12
0
0
11
11
11
1
11
0
10
10
10
1
10
0
SYSCNTL (R/W)
PWM
MODE
SPORT1 CONFIGURE
MODECTRL (R/W)
MEMWAIT (R/W)
SYSSTAT (R)
9
0
9
9
9
0
PWM PHASE
FLAG
8
0
8
8
8
0
7
7
0
7
0
7
6
0
6
6
0
6
0
5
5
0
5
0
5
0
0
0
4
4
4
4
0
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SERIAL PORT
DATA RECEIVE
SELECT
3
3
0
3
3
0
SPORT1
MODE
2
2
2
0
2
0
1
1
0
1
1
0
0
0
0
0
0
0
1 = DR1B
0 = DR1A
1 = UART MODE
0 = SPORT MODE
PWMTRIP
PIN STATE
PWMPOL
PIN STATE
WATCHDOG
FLAG
DM (0x2016)
DM (0x3FFF)
DM (0x3FFE)
DM (0x2015)
1 = HI
0 = LO
1 = WATCHDOG TRIP
0 = NO WATCHDOG TRIP
1 = HI = > ACTIVE HI
0 = LO = > ACTIVE LO
ADMC300

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