C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 68
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C509-L_97
Manufacturer Part Number
C509-L_97
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C509-L_97.pdf
(290 pages)
- Current page: 68 of 290
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The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri
instructions. If the address formed by XPAGE and Ri points outside the XRAM address range, an
external access is performed. For the C509-L the contents of XPAGE must be greater or equal F3 H
in order to use the XRAM/.
Thus, the register XPAGE is used for addressing of the XRAM; additionally its contents are used
for generating the internal XRAM select. If the contents of XPAGE is less than the XRAM address
range then an external bus access is performed where the upper address byte is provided by P2
and not by XPAGE!
The software has to distinguish two cases, if the MOVX @Ri instructions with paging shall be used:
a) Access to XRAM:
b) Access to external memory:
4.4.4
The content of the XRAM is not affected by a reset. After power-up the content is undefined, while
it remains unchanged during and after a reset as long as the power supply is not turned off. If a reset
occurs during a write operation to XRAM, the content of a XRAM memory location depends on the
cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction):
Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected.
Reset during 2nd cycle : The old value in XRAM is overwritten by the new value.
4.4.5 Behaviour of Port0 and Port2
The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register
SYSCON and on the state of pin EA. The table 4-1 lists the various operating conditions. It shows
the following characteristics:
The shaded areas describe the standard operation as each 80C51 device without on-chip XRAM
behaves.
Semiconductor Group
a) Use of P0 and P2 pins during the MOVX access.
b) Activation of the RD and WR pin during the access.
c) Use of internal or external XDATA memory.
Bus: The pins work as external address/data bus. If (internal) XRAM is accessed, the data
I/0:
Reset Operation of the XRAM
The pins work as Input/Output lines under control of their latch.
written to the XRAM can be seen on the bus in debug mode.
The upper address byte must be written to XPAGE or P2;
both writes select the XRAM address range.
The upper address byte must be written to P2; XPAGE will be
loaded with the same address in order to deselect the XRAM.
4-16
External Bus Interface
1997-10-01
C509-L
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