C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 63

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

External Bus Interface
C509-L
After a reset operation, bit XMAP0 is reset. This means that the accesses to the XRAM is generally
disabled. In this case, all accesses using MOVX instructions with an address in the range of F400 H
to FFFF H generate external data memory bus cycles. When XMAP0 is set, the access to the XRAM
is enabled and all accesses using MOVX instructions with an address in the range of F400 H to
FFFF H will access internally the XRAM.
Bit XMAP0 is hardware protected. If it is reset once (XRAM access enabled) it cannot be set by
software. Only a reset operation will set the XMAP0 bit again. This hardware protection mechanism
is done by an unsymmetric latch at the XMAP0 bit. A unintentional disabling of XRAM could be
dangerous since indeterminate values could be read from external bus. To avoid this the XMAP0 bit
is forced to '1' only by a reset operation. Additionally, during reset an internal capacitor is loaded. So
the reset state is a disabled XRAM. Because of the load time of the capacitor, XMAP0 bit once
written to '0' (that is, discharging the capacitor) cannot be set to '1' again by software. On the other
hand any distortion (software hang up, noise,...) is not able to load this capacitor, too. That is, the
stable status is XRAM enabled.
The clear instruction for the XMAP0 bit should be integrated in the program initialization routine
before the XRAM is used. In extremely noisy systems the user may have redundant clear
instructions.
Semiconductor Group
4-11
1997-10-01