C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 189

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

6.6.3 A/D Converter Clock Selection
The ADC uses basically three clock signals for operation: the input clock f
clock f
C509-L system clock f
while the conversion clock and the sample clock must be adapted. The conversion clock is limited
to a maximum frequency of 2 MHz. Therefore, the conversion clock prescaler must be programmed
to a value which assures that the conversion clock does not exceed 2 MHz. The prescaler ratio of
the conversion clock is selected by the bits ADCL1 and ADCL0 of SFR ADCON1. The sample clock
f
The prescaler ratio of the sample clock is selected by the bits ADST1 and ADST0 of SFR ADCON1.
Figure 6-48 shows the configuration of the two A/D converter prescalers. The table in figure 6-48
defines the divider ratio for the conversion and sample clock of each combination of the prescaler
bits.
Figure 6-48
A/D Converter Clock Selection
The duration of an A/D conversion is a multiple of the period of the f
the A/D conversion and the calculation of an A/D conversion time are shown in the next section.
Semiconductor Group
SC
Conversion Clock f
ADCL1 ADCL0 f
can be adapted to the requirements of the impedance of A/D converter input signal sources.
ADC
0
0
1
1
(=1/t
0
1
0
1
ADC
ADC
) and the sample clock f
ADC
f
f
f
f
IN
IN
OSC
IN
IN
/ 16
/ 32
/ 4
/ 8
which is applied at the XTAL pins. The input clock f
Sample Clock f
ADST1 ADST0
0
f
f
f
f
IN
IN
IN
IN
/ 16
/ 32
/ 64
/ 8
0
SC
SC
6-111
ADST1 ADST0
0
(=1/t
f
f
f
f
IN
IN
IN
IN
/ 128
/ 16
/ 32
/ 64
SC
On-Chip Peripheral Components
). All clock signals are derived from the
1
ADST1 ADST0
1
f
f
f
f
IN
IN
IN
IN
IN
/ 128
/ 256
/ 32
/ 64
clock signal. The timing of
IN
0
(=1/t
ADST1 ADST0
IN
IN
), the conversion
is equal to f
1
f
f
f
f
IN
IN
IN
IN
/ 128
/ 256
/ 512
/ 64
1997-10-01
C509-L
1
OSC