C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 193
C509-L_97
Manufacturer Part Number
C509-L_97
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C509-L_97.pdf
(290 pages)
- Current page: 193 of 290
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Depending on the application, typically there are three software methods to handle the A/D
conversion in the C509-L.
Depending on the oscillator frequency of the C509-L and the selected divider ratios of the A/D
converter prescalers the total time of an A/D conversion is calculated according to table 6-13. The
minimum conversion time is 6 s.
Table 6-13
A/D Conversion Times
Conversion Clock
Note : The shaded prescaler/frequency combinations must not be used. Reason : f
Semiconductor Group
ADCL1
– Software delay
– Polling BSY bit
– A/D conversion interrupt
0
0
1
1
Prescaler
The machine cycles of the A/D conversion are counted and the program executes a software
delay (e.g. NOPs) before reading the A/D conversion result in the write result cycle. This is
the fastest method to get the result of an A/D conversion.
The BSY bit is polled and the program waits until BSY=0. Attention : a polling JB instruction
which is two machine cycles long, possibly may not recognize the BSY=0 condition during the
write result cycle in the continuous conversion mode.
After the start of an A/D conversion the A/D converter interrupt is enabled. The result of the
A/D conversion is read in the interrupt service routine. If other SAB-C509 interrupts are
enabled, the interrupt latency must be regarded. Therefore, this software method is the
slowest method to get the result of an A/D conversion.
ADCL0
0
1
0
1
Sample Clock
ADST1 ADST0
Prescaler
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.875 13.7
0.438 27.4
0.219 54.9
0.109 109.7
[MHz]
f
ADC
3.5 MHz
16
20.6
29.7
32
41.1
59.4
64
82.3
118.9
128
164.6
237.7
6-115
t
ADCC
[ s]
2
1
0.5
0.25
[MHz]
f
On-Chip Peripheral Components
ADC
Processor Clock Rate
8 MHz
6
7
9
13
12
14
18
26
24
28
36
52
48
56
72
104
t
ADCC
[ s]
3
1.5
0.75
0.375 32
[MHz]
f
ADC
12 MHz
4
4.7
6
8.7
8
9.3
12
17.3
16
18.7
24
34.7
37.3
48
69.3
t
ADCC
[ s]
ADC
4
2
1
0.5
[MHz]
f
> 2 MHz.
ADC
1997-10-01
16 MHz
C509-L
3
3.5
4.5
6.5
6
7
9
13
12
14
18
26
24
28
36
52
t
ADCC
[ s]
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