C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 220

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

8.1.1 Input Clock Selection
The input clock rate of the watchdog timer is derived from the system clock of the C509-L. There are
two prescalers which define the input clock rate. These prescalers are controlled by two bits in the
SFRs PRSC and WDTREL. Table 8-1 shows the resulting timeout periods at
Special Function Register PRSC (Address B4 H )
Special Function Register WDTREL (Address 86 H )
Bit
WDTP
WPSEL
WDTREL.6-0
Table 8-1
Watchdog Timer Timeout Periods at
WDTREL
00 H
7E H
7F H
Semiconductor Group
Bit No.
B4 H
86 H
f
24.6 ms
381 s
189 s
OSC
The shaded bits are not used for the watchdog timer.
WPSEL
WDTP
/12
MSB
Function
Prescaler select bits for the watchdog input clock
The two control bits WDTP and WPSEL define the input clock frequency
the watchdog timer.
Watchdog timer reload value
Seven bit reload value for the high-byte of the watchdog timer. This value is
loaded to the WDT when a refresh is triggered by a consecutive setting of bits
WDT and SWDT.
7
WDTP
0
0
1
1
7
f
49.1 ms
762 s
378 s
Time-Out Periods
OSC
S0P
6
/24
6
WPSEL
0
1
0
1
T2P1
f
393 ms
6.10 ms
3.02 ms
OSC
5
5
/192
Watchdog timer reload value
f
OSC
T2P0
= 16 MHz
4
Input clock
4
f
f
f
f
f
786 ms
12.2 ms
6.05 ms
IN
IN
IN
IN
OSC
8-2
=
=
=
=
/384
f
f
f
f
OSC
OSC
OSC
OSC
T1P1
3
3
/12
/192
/24 (reset value)
/384
Comments
Maximum time period (default after reset)
(128 WDTL overflows)
Two WDTL overflows
Min. time period (One WDTL overflow)
T1P2
2
2
T0P1
Fail Save Mechanisms
1
1
Reset Value : 11010101 B
T0P0
LSB
f
0
OSC
0
Reset Value : 00 H
= 16 MHz.
WDTREL
PRSC
1997-10-01
C509-L
f
IN
of