C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 286
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C509-L_97
Manufacturer Part Number
C509-L_97
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C509-L_97.pdf
(290 pages)
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D
Semiconductor Group
COMSETH . . . . . . . . . . . . . . . . 3-21, 3-24
COMSETL . . . . . . . . . . . . . . . . . 3-21, 3-23
CPU
CRCH . . . . . . . . . . . . . . . . 3-21, 3-25, 6-35
CRCL . . . . . . . . . . . . . . . . 3-21, 3-25, 6-35
CT1CON . . . . 3-19, 3-21, 3-24, 6-39, 7-16
CT1F . . . . . . . . . . . . . . . . . 3-24, 6-40, 7-16
CT1P . . . . . . . . . . . . . . . . . . . . . 3-24, 6-40
CT1RELH . . . . . . . . . . . . . 3-21, 3-26, 6-41
CT1RELL . . . . . . . . . . . . . 3-21, 3-26, 6-41
CTCON . 3-19, 3-21, 3-26, 6-33, 6-39, 7-16
CTF . . . . . . . . . . . . . . . . . . 3-26, 6-39, 7-16
CTP . . . . . . . . . . . . . . . . . . . . . . 3-26, 6-40
CTRELH . . . . . . . . . . . . . . 3-21, 3-26, 6-41
CTRELL . . . . . . . . . . . . . . 3-21, 3-26, 6-41
CY . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-25
Data memory . . . . . . . . . . . . . . . . . . . . 3-2
Datapointers . . . . . . . . . . . . . . . . 4-6 to 4-9
DC characteristics . . . . . . . . . . 11-1 to 11-6
Device Characteristics . . . . . 11-1 to 11-13
DIR0 . . . . . . . . . . . . . . . . . . 3-22, 3-23, 6-4
DIR1 . . . . . . . . . . . . . . . . . . 3-22, 3-23, 6-4
DIR2 . . . . . . . . . . . . . . . . . . 3-22, 3-23, 6-4
DIR3 . . . . . . . . . . . . . . . . . . 3-22, 3-24, 6-4
DIR4 . . . . . . . . . . . . . . . . . . 3-22, 3-26, 6-4
DIR5 . . . . . . . . . . . . . . . . . . 3-22, 3-27, 6-4
DIR6 . . . . . . . . . . . . . . . . . . 3-22, 3-27, 6-4
DIR9 . . . . . . . . . . . . . . . . . . 3-22, 3-27, 6-4
Direction registers . . . . . . . . . . . . . . . . . 6-4
Compare timer 1 operation . 6-65 to 6-68
Table of CCU SFRs . . . . . . . . . . . . . 6-31
Accumulator . . . . . . . . . . . . . . . . . . . 2-3
B register . . . . . . . . . . . . . . . . . . . . . . 2-4
Basic timing . . . . . . . . . . . . . . . . . . . . 2-5
Fetch/execute diagram . . . . . . . . . . . 2-6
Functionality . . . . . . . . . . . . . . . . . . . 2-3
Stack pointer . . . . . . . . . . . . . . . . . . . 2-4
Access mechanism . . . . . . . . . . . . . . 4-7
Basic operation . . . . . . . . . . . . . . . . . 4-6
Example using multiple DPTRs . . . . . 4-9
Example using one DPTR . . . . . . . . . 4-8
Select register DPSEL . . . . . . . . . . . . 4-6
Using CM0 to CM7 . . . . . 6-59 to 6-63
Using interrupts . . . . . . . . 6-71 to 6-74
Capture function . . . . . . . . . . . . . 6-68
Compare function . . . . . . . . . . . . 6-66
12-3
E
DPH . . . . . . . . . . . . . . . . . . . . . 3-19, 3-23
DPL . . . . . . . . . . . . . . . . . . . . . 3-19, 3-23
DPSEL . . . . . . . . . . . . . . . . 3-19, 3-23, 4-6
EA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
EA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
EADC . . . . . . . . . . . . . . . . 3-24, 6-110, 7-7
EAL . . . . . . . . . . . . . . . . . . . . . . . 3-24, 7-6
ECC1 . . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
ECMP . . . . . . . . . . . . . . . . . 3-23, 6-73, 7-8
ECR . . . . . . . . . . . . . . . . . . 3-23, 6-73, 7-8
ECS . . . . . . . . . . . . . . . . . . 3-23, 6-73, 7-8
ECT . . . . . . . . . . . . . . . . . . 3-23, 6-73, 7-8
ECT1 . . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
EICC1 . . . . . . . . . . . . 3-19, 3-24, 6-73, 7-9
EICC10 . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
EICC11 . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
EICC12 . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
EICC13 . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
EICC14 . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
EICC15 . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
EICC16 . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
EICC17 . . . . . . . . . . . . . . . . 3-24, 6-73, 7-9
Emulation concept . . . . . . . . . . . . . . . . 4-5
ES0 . . . . . . . . . . . . . . . . . . . . . . . 3-24, 7-6
ES1 . . . . . . . . . . . . . . . . . . . . . . . 3-23, 7-8
ESWC . . . . . . . . . . . . . . . . 3-10, 3-13, 3-24
ET0 . . . . . . . . . . . . . . . . . . . 3-24, 6-20, 7-6
ET1 . . . . . . . . . . . . . . . . . . . 3-24, 6-20, 7-6
ET2 . . . . . . . . . . . . . . . . . . . 3-24, 6-34, 7-6
EX0 . . . . . . . . . . . . . . . . . . . . . . . 3-24, 7-6
EX1 . . . . . . . . . . . . . . . . . . . . . . . 3-24, 7-6
EX2 . . . . . . . . . . . . . . . . . . . . . . . 3-24, 7-7
EX3 . . . . . . . . . . . . . . . . . . . . . . . 3-24, 7-7
EX4 . . . . . . . . . . . . . . . . . . . . . . . 3-24, 7-7
EX5 . . . . . . . . . . . . . . . . . . . . . . . 3-24, 7-7
EX6 . . . . . . . . . . . . . . . . . . . . . . . 3-24, 7-7
Execution of instructions . . . . . . . 2-5, 2-6
EXEN2 . . . . . . . . . . . . . . . . 3-24, 6-35, 7-7
EXF2 . . . . . . . . . . . . . . . . 3-24, 6-35, 7-14
External bus interface . . . . . . . . . . . . . . 4-1
ALE signal . . . . . . . . . . . . . . . . . . . . . 4-4
Overlapping of data/program memory 4-2
Program memory access . . . . . . . . . 4-2
Program/data memory timing . . . . . . 4-3
PSEN signal . . . . . . . . . . . . . . . . . . . 4-2
Role of P0 and P2 . . . . . . . . . . . . . . . 4-1
1997-10-01
C509-L
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