bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 56

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

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2.0 Electrical Interfaces
2.1 Input Interface
2.1.3 Autodetection of NTSC or PAL/SECAM Video
2.1.4 Flash A/D Converters
2.1.5 A/D Clamping
2.1.6 Power-Up Operation
If the Bt829B is configured to decode both NTSC and PAL/SECAM, the Bt829B
can be programmed to automatically detect which format is being input to the
chip. Autodetection will select the proper clock source for the detected format. If
NTSC/PAL–M is detected, XTAL0 is selected. If PAL/SECAM is detected,
XTAL1 is selected. For PAL-N combination the user must manually select the
XTAL0 crystal. Full control of the decoding configuration can be programmed by
writing to the Input Format Register (0x01).
number of lines in a frame. Bit NUML indicates the result in the STATUS regis-
ter. Based on this bit, the format of the video is determined, and XT0 or XT1 is
selected for the clock source. Automatic format detection will select the clock
source, but it will not program the required registers. The scaling and cropping
registers (VSCALE, HSCALE, VDELAY, HDELAY, VACTIVE, and HACTIVE),
as well as the burst delay and AGC delay registers (BDELAY and ADELAY)
must be programmed accordingly.
The Bt829B and Bt827B use two on-chip flash A/D converters to digitize the
video signals. YREF+, CREF+, YREF–, and CREF– are the respective top and
bottom of the internal resistor ladder.
connected to analog ground. The voltage levels for YREF+ and CREF+ are
controlled by the gain control circuitry. If the input video momentarily exceeds
the corresponding REF+ voltage, it is indicated by LOF and COF in the STATUS
register.
An internally generated clamp control signal is used to clamp the inputs of the
A/D converter for DC restoration of the video signals. Clamping for both the YIN
and CIN analog inputs occurs within the horizontal sync tip. The YIN input is
always restored to ground while the CIN input is always restored to CLEVEL.
CLEVEL can be set with an optional external resistor network so that it is biased
to the midpoint between CREF– and CREF+. This ensures backward compatibil-
ity with the Bt819A/7A/5A, but is not required for the Bt829B/827B. External
clamping is not required because internal clamping is automatically performed.
Upon power-up, the status of the Bt829B’s registers is indeterminate. The RST
signal must be asserted to set the register bits to their default values. The Bt829B
device defaults to NTSC-M format upon reset. If pin 85 (OEPOLE) is tied to a
logical high on power-up and the RST signal is asserted, then the video pixel bus,
sync signals, and output clocks will be three-stated.
The Bt829B determines the video source input to the chip by counting the
The input video is always AC-coupled to the decoder. CREF– and YREF– are
D829BDSA
VideoStream II Decoders
Bt829B/827B