bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 111

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

Bt829B
VideoStream II Decoders
0x1B—Video Timing Control (VTC)
This register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00. VFILT(0) is
the LSB. An asterisk indicates the default option.
HSFMT
ACTFMT
CLKGATE
VBIEN
VBIFMT
VALIDFMT
HSFMT
7
0
This bit selects between a single-pixel-wide HRESET and the standard 64-clock-wide
HRESET.
This bit selects whether composite ACTIVE (HACTIVE and VACTIVE) or whether
HACTIVE only is output on the ACTIVE pin.
This bit selects the signals that are gated with CLK to create QCLK. If logical 0 is selected, the
ACTIVE pin (composite ACTIVE or HACTIVE) is used in gating CLK.
This bit enables VBI data to be captured.
This bit determines the byte ordering for VBI data.
ACTFMT
6
0
CLKGATE
5
0
0*
1
0*
1
0*
1
0*
1
0*
1
0*
1
=
=
=
=
=
=
=
=
=
=
=
=
VBIEN
HRESET is 64 CLKx1 cycles wide
HRESET is 1 pixel wide
ACTIVE is composite active
ACTIVE is horizontal active
CLKx1 and CLKx2 are gated with DVALID and ACTIVE to
create QCLK
CLKx1 and CLKx2 are gated with DVALID to create QCLK
Do not capture VBI
Capture VBI
Pixel N on the VD[15:8] data bus, pixel N+1 on the VD[7:0]
data bus
Pixel N+1 on the VD[15:8] data bus, Pixel N on the VD[7:0]
data bus (Pixel N refers to the first, third, fifth, and so on, while
pixel N+1 refers to the second, fourth, and sixth in a horizontal
line of video)
Normal DVALID timing
DVALID is the logical AND of VALID and ACTIVE, where
ACTIVE is controlled by the ACTFMT bit. Also, the QCLK
signal will free turn and is an inverted version of CLKx1 or
CLKx2, depending upon whether 8- or 16-bit pixel output
format is selected.
4
0
D829BDSA
VBIFMT
3
0
VALIDFMT
2
0
4.0 Control Register Definitions
0x1B—Video Timing Control (VTC)
1
0
VFILT
0
0
101