bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 110

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

100
4.0 Control Register Definitions
0x1A—ADC Interface Register (ADC)
0x1A—ADC Interface Register (ADC)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x82.
Reserved is the LSB. An asterisk indicates the default option.
Reserved
SYNC_T
AGC_EN
CLK_SLEEP
Y_SLEEP
C_SLEEP
CRUSH
7
1
Reserved
These bits should only be written with bit 7 set at a logical 1 and bit 6 set at a logical 0.
This bit defines the voltage level for which the SYNC signal can be detected.
This bit controls the AGC function. When disabled, REFOUT is not driven, and an external
reference voltage must be provided. When enabled, REFOUT is driven to control the A/D
reference voltage.
When this bit is set at a logical 1, the system clock is powered down, but the output clocks
(CLKx1 and CLKx2) are still running, and the I
is approximately one second.
This bit enables the luma ADC to operate in sleep mode.
This bit enables the chroma ADC to operate in sleep mode.
This bit enables white CRUSH mode, and must be written with a logical 0.
6
0
SYNC_T
5
0
0*
1
0*
1
0*
1
0*
1
0
1*
0*
1
=
=
=
=
=
=
=
=
=
=
=
=
AGC_EN
Analog SYNCDET threshold high (~125 mV)
Analog SYNCDET threshold low (~75 mV)
AGC Enabled
AGC Disabled
Normal clock operation
Shut down the system clock (power down)
Normal Y ADC operation
Sleep Y ADC operation
Normal C ADC operation
Sleep C ADC operation
Normal SYNC level to white level
Enable white CRUSH mode to compensate for nonstandard
SYNC to white video relationship
4
0
D829BDSA
CLK_SLEEP
3
0
2
C registers are still accessible. Recovery time
Y_SLEEP
2
0
C_SLEEP
VideoStream II Decoders
1
1
CRUSH
Bt829B
0
0